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Smart Cache
Smart Cache is a level 2 or level 3 caching method for multiple execution cores, developed by Intel. Smart Cache shares the actual cache memory…
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11 relations
CPU cache
Haswell (microarchitecture)
List of Intel Celeron microprocessors
List of Intel Core i3 microprocessors
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Broader (3)
Cache (computing)
Central processing unit
Computer memory
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
Smart-Cache: Optimising Memory Accesses for Arbitrary Boundaries and Stencils on FPGAs
S. Nabi
,
W. Vanderbauwhede
IEEE International Symposium on Parallel…
2019
Corpus ID: 181461797
A key requirement for high performance on FPGAs is to maintain continuous data streaming from the DRAM. An impediment in many…
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2019
2019
A Smart Cache Strategy for Tag-Based Browsing of Digital Collections
Joaquín Gayoso-Cabada
,
Mercedes Gómez-Albarrán
,
J. Sierra
WorldCIST
2019
Corpus ID: 92999189
Tag-based browsing is a common interaction technique in business, the culture industry and many other domains. According to this…
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2019
2019
A Case for Two-stage Inference with Knowledge Caching
Geonha Park
,
Changho Hwang
,
KyoungSoo Park
EMDL '19
2019
Corpus ID: 190231556
Real-world intelligent services employing deep learning technology typically take a two-tier system architecture -- a dumb front…
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2012
2012
NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution
Kaveh Aasaraai
,
Andreas Moshovos
International Journal of Reconfigurable Computing
2012
Corpus ID: 7946090
Soft processors often use data caches to reduce the gap between processor and main memory speeds. To achieve high efficiency…
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2012
2012
A Smart Cache Designed for Embedded Applications
Afrin Naz
,
K. Kavi
2012
Corpus ID: 18271683
In this paper, we extend our previous investigation of split array and scalar data caches to embedded systems. More specifically…
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2011
2011
A reconfigurable cache architecture for energy efficiency
Karthik T. Sundararajan
,
Timothy M. Jones
,
N. Topham
ACM International Conference on Computing…
2011
Corpus ID: 10558467
On-chip caches often consume a significant fraction of the total processor energy budget. Allowing adaptation to the running…
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Review
2011
Review
2011
A Parallel Transaction-Level Model of H.264 Video Decoder
Xu Han
,
Weiwei Chen
,
R. Doemer
2011
Corpus ID: 59891469
H.264 video decoder is a computationally demanding application. In resource-limited embedded environment, it is desirable to…
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2008
2008
Cycle-time-aware sequential way-access set-associative cache for low energy consumption
Chih-Hui Ting
,
Juinn-Dar Huang
,
Yu-Hsiang Kao
Asia Pacific Conference on Circuits and Systems
2008
Corpus ID: 1761302
In this paper, we exploit the concept of sequential way access to reduce the number of ways being activated on each access of set…
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1998
1998
User-oriented smart-cache for the Web: what you seek is what you get!
Z. Lacroix
,
Arnaud Sahuguet
,
Raman Chandrasekar
ACM SIGMOD Conference
1998
Corpus ID: 12847148
Standard database approaches to querying information on the Web focus on the source(s) and provide a query language based on a…
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1995
1995
A 2.25 gbytes/s 1 Mbit smart cache SRAM
J. Ku
,
S. Siu
,
M. Yazdani
,
Yolin Lih
,
Wei Lu
,
A. Desroches
Digest of Technical Papers., Symposium on VLSI…
1995
Corpus ID: 61021660
The wide-word architecture is widely regionized as the next generation CPU architecture by most of the system vendors. This type…
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