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Serial binary adder

Known as: Serial adder, Serial binary adders, Serial binary subtracter 
The serial binary adder or bit-serial adder is a digital circuit that performs binary addition bit by bit. The serial full adder has three single-bit… 
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Related topics

Related topics

3 relations
Flip-flop (electronics)Ones' complementTwo's complement

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Efficient digit serial architecture for sign based least mean square adaptive filter for denoising of artefacts in ECG signals
Variants of Least Mean Square algorithm, namely the Sign Error, Sign Regressor and Sign-Sign Least Mean Square algorithms are… 
2016
2016
LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder
As the chip size is getting decreased with the advent of technology, power dissipation has become a major issue to the circuit… 
2013
2013
Designing and Characterization of koggestone, Sparse Kogge stone, Spanning tree and Brentkung Adders
Adders are known to be the frequently used ones in VLSI designs. In digital design we have half adder and full adder, by using… 
2012
2012
Design and Implementation of FPGA based Low Power Digital FIR Filter
Abstract : Finite impulse response (FIR) filters are widely used in various DSP applications. The low-power or low-area… 
2012
2012
Novel asynchronous registers for sequential circuits with quantum-dot cellular automata
Quantum-dot cellular automata (QCA) are nano-scale devices for implementing logic circuits. The disadvantage of QCA circuits is… 
Highly Cited
2007
Highly Cited
2007
Robust Adders Based on Quantum-Dot Cellular Automata
This paper demonstrates designing adders on quantum-dot cellular automata (QCA) nanotechnology, which offers a way to implement… 
2004
2004
A method for increasing the throughput of fixed coefficient digit-serial/parallel multipliers
Fixed coefficient digit-serial/parallel multipliers are presented. The multipliers are based on unfolded bit-serial/parallel… 
1996
1996
Power consumption and performance of low-voltage bit-serial adders
  • T. NjølstadE. Aas
  • IEEE International Symposium on Circuits and…
  • 1996
  • Corpus ID: 61967193
By comparative simulations and chip measurements we have found that swing-restored pass transistor logic (SRPL) are suitable for… 
1995
1995
Highly parallel computers for artificial neural networks
During a number of years the two fields of artificial neural networks (ANNs) and highly parallel computing have both evolved… 
1994
1994
Radix digit-serial pipelined divider/square-root architecture
The paper presents a new digit-serial architecture for division and square-root which can be pipelined to the bit level to… 
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