Skip to search formSkip to main contentSkip to account menu

Serial binary adder

Known as: Serial adder, Serial binary adders, Serial binary subtracter 
The serial binary adder or bit-serial adder is a digital circuit that performs binary addition bit by bit. The serial full adder has three single-bit… 
Wikipedia (opens in a new tab)

Related topics

Related topics

3 relations
Flip-flop (electronics)Ones' complementTwo's complement

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Novel Optimized Designs for QCA Serial Adders
Quantum-dot Cellular Automata (QCA) is a new and efficient technology to implement logic Gates and digital circuits at the… 
2015
2015
Design of digit serial FIR Filter for power optimization
The low power digital FIR Filter depending on digit serial adder and multiple constant multiplier (MCM) is explained in this… 
2013
2013
TECHNOLOGY Comparison between Serial Adder and Parallel Adder
In digital circuit addition process is biggest and very important process. With the help of this meth od digital equipment… 
2013
2013
Implementation of Low Power Digital FIR Filter Design Based on low power multipliers and adders
Abstract-This paper presents the methods to reduce dynamic power consumption of a digital Finite Impulse Response (FIR) filter… 
2012
2012
Novel asynchronous registers for sequential circuits with quantum-dot cellular automata
Quantum-dot cellular automata (QCA) are nano-scale devices for implementing logic circuits. The disadvantage of QCA circuits is… 
2007
2007
Efficient Design of QCA Adder Structures
Optimizing arithmetic primitives such as quantum-dot cellular automata (QCA) adders is important for investigating high… 
2005
2005
Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures
In this paper we analyse a serial (ripple carry) and a parallel (Kogge-Stone) adder when operating in subthreshold at 100nm and… 
2004
2004
A method for increasing the throughput of fixed coefficient digit-serial/parallel multipliers
Fixed coefficient digit-serial/parallel multipliers are presented. The multipliers are based on unfolded bit-serial/parallel… 
1995
1995
Highly parallel computers for artificial neural networks
During a number of years the two fields of artificial neural networks (ANNs) and highly parallel computing have both evolved… 
1995
1995
Ultra Low Energy Computing Using Adiabatic Switching Principle
This paper presents a new family of logic gates for ultra low energy computing using pulsed power CMOS logic. The logic gates use… 
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)