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VLSI implementations of threshold logic-a comprehensive survey
TLDR
This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades and detail numerous very-large-scale integration (VLSI) implementations including capacitive, conductance/current, and pseudo-nMOS and output-wired-inverters, as well as many differential solutions. Expand
Using Bayesian Networks to Accurately Calculate the Reliability of Complementary Metal Oxide Semiconductor Gates
TLDR
An EDA tool is introduced that quickly and accurately estimates the reliability of any CMOS gate by taking into consideration the gate's topology,the reliability of the individual devices, the applied input vector, as well as the noise margins. Expand
Differential implementations of threshold logic gates
This paper reviews differential implementations of threshold logic gates, detailing two classes of solutions: capacitive (switched capacitor and floating gate), and conductance/current.
On the Exact Reliability Enhancements of Small Hammock Networks
In this paper, we study small hammock networks, more precisely the 29 hammock networks presented by Moore and Shannon in their prescient paper from 1956, where this type of network was introduced. WeExpand
VLSI complexity reduction by piece-wise approximation of the sigmoid function
TLDR
It is shown that there are simple and accurate ways to compute a sigmoid nonlinearity in digital hardware by piece-wise linearization by detail such an approximation algorithm, and analyze its accuracy, showing improvements over the previous known algorithms. Expand
Characterization of a 16-bit threshold logic single-electron technology adder
TLDR
The design of an optimal TLG adder implemented in SET is presented, fully designed and simulated using a Monte Carlo simulator to give a quantitative estimate of both the delay and the power dissipation of the adder. Expand
Multiplexing schemes for cost-effective fault-tolerance
  • S. Roy, Valeriu Beiu
  • Computer Science
  • 4th IEEE Conference on Nanotechnology, .
  • 16 August 2004
TLDR
It is shown that MAJ-3 vN-MUX performs very well when compared to other redundancy schemes, and an extension is described that contributes up to four more orders of magnitude, by excluding superfluous restorative stages for very small redundancy factors. Expand
On the Circuit Complexity of Sigmoid Feedforward Neural Networks
TLDR
The main conclusion is that there are interesting fan-in dependent depth-size tradeoffs when trying to digitally implement sigmoid activation feedforward neural networks. Expand
Split-Precharge Differential Noise-Immune Threshold Logic Gate (SPD-NTL)
After a short review of the state-of-the-art, a new low-power differential threshold logic gate is introduced: split-precharge differential noiseimmune threshold logic(SPD-NTL). It is based onExpand
Digital integrated circuit implementations
TLDR
There is considerable computational and physiological justification that shallow threshold gate circuits are computationally more efficient than classical Boolean circuits, and the ‘VLSI-friendly learning algorithms’ are mentioned as a promising direction of research. Expand
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