Skip to search formSkip to main contentSkip to account menu

Repeater insertion

Repeater insertion is a technique for reducing the time delay associated with long wire lines in integrated circuits. The technique involves cutting… 
Wikipedia (opens in a new tab)

Related topics

Related topics

3 relations
Electronic circuitIntegrated circuitRC circuit

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars
This paper proposes a highly dense reconfigurable architecture that introduces via-switch device, which is a nonvolatile… 
2012
2012
Ultra-low-power signaling challenges for subthreshold global interconnects
2008
2008
Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects
The simultaneous application of voltage scaling, repeater insertion, and wire sizing is proposed in this paper to achieve high… 
2008
2008
Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion
Capacitive crosstalk between adjacent signal wires has significant effect on performance and delay uncertainty of point-to-point… 
2004
2004
Frequency driven repeater insertion for deep submicron
Repeaters now widely used to decrease delay and increase the performance of long interconnects. The maximum operating frequency… 
Highly Cited
2000
Highly Cited
2000
Repeater insertion in deep sub-micron CMOS: ramp-based analytical model and placement sensitivity analysis
Repeaters are now widely used to increase the performance of long on-chip interconnections in CMOS VLSI. In this paper, we take… 
Highly Cited
1999
Highly Cited
1999
Repeater insertion in tree structured inductive interconnect
The effects of inductance on repeater insertion in RLC trees is the focus of the paper. An algorithm is introduced to insert and… 
Highly Cited
1999
Highly Cited
1999
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits: A summary
A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5… 
1999
1999
Noise-aware repeater insertion and wire-sizing for on-chip interconnect using hierarchical moment-matching
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the… 
1998
1998
Optimum repeater insertion based on a CMOS delay model for on-chip RLC interconnect
A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 7… 
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)