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RISC-V
Known as:
RISC V
, RISC-V architecture
, RISCV
RISC-V (pronounced "risk-five") is an open-source instruction set architecture (ISA) based on established reduced instruction set computing (RISC…
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Related topics
Related topics
50 relations
128-bit
AVX-512
Advanced Vector Extensions
Assembly language
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
Open-Source Validation Suite for RISC-V
M. Chupilko
,
A. Kamkin
,
Alexander Protsenko
International Workshop on Microprocessor Test and…
2019
Corpus ID: 212645869
In this paper, we propose a validation suite, applicable for different RISC-V designs. The suite can be considered as a stack of…
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2019
2019
RISC-V: #AlphanumericShellcoding
Hadrien Barral
,
Rémi Géraud-Stewart
,
Georges-Axel Jaloyan
,
D. Naccache
WOOT @ USENIX Security Symposium
2019
Corpus ID: 199543502
We explain how to design RISC-V shellcodes capable of running arbitrary code, whose ASCII binary representation use only letters…
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2019
2019
A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing
C. Sudarshan
,
J. Lappas
,
C. Weis
,
Deepak M. Mathew
,
Matthias Jung
,
N. Wehn
International Conference / Workshop on Embedded…
2019
Corpus ID: 199501788
Energy consumption is one of the major challenges for the advanced System on Chips (SoC). This is addressed by adopting…
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2019
2019
RVTensor: A Light-Weight Neural Network Inference Framework Based on the RISC-V Architecture
Pengpeng Hou
,
Jiageng Yu
,
Yuxia Miao
,
Yang Tai
,
Y. Wu
,
Chen Zhao
BenchCouncil International Symposium
2019
Corpus ID: 219561086
The open-source instruction set architecture RISC-V has developed rapidly in recent years, and its combination mode of multiple…
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2019
2019
PERI: A Posit Enabled RISC-V Core
Sugandha Tiwari
,
Neel Gala
,
C. Rebeiro
,
V. Kamakoti
arXiv.org
2019
Corpus ID: 199441879
Owing to the failure of Dennard's scaling the last decade has seen a steep growth of prominent new paradigms leveraging…
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2018
2018
Hardware and protocols for authentication and secure computation
C. Juvekar
2018
Corpus ID: 58267379
The Internet of Things has resulted in an exponential rise in the number of embedded electronic devices. This thesis deals with…
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2018
2018
Chi re : A Configurable Hardware Fault Injection Framework for RISC-V Systems
Schuyler Eldridge
2018
Corpus ID: 53059502
The application of modern software design approaches to hardware design has increased the speed at which teams can move and the…
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2014
2014
Micro-Policies A Framework for Verified, Hardware-Assisted Security Monitors
Arthur Azevedo de Amorim
,
B. Pierce
,
Antal Spector-Zabusky
,
A. Tolmach
2014
Corpus ID: 53994953
A wide range of low-level security policies can be expressed as rules on metadata tags and enforced using a combination of a…
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2008
2008
A RISC CPU IP core
P. Ye
,
Chaodong Ling
International Conference on Anti-counterfeiting…
2008
Corpus ID: 16004340
This article describes the hardware design of a RISC CPU IP core whose instructions are compatible with the Microchip PIC16C6X…
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1990
1990
RISC 프로세서 연산장치부의 설계 ( The Design of A RISC Processor`s ALU )
김대영
,
한충석
,
+4 authors
임인칠
1990
Corpus ID: 61947576
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