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RISC-V

Known as: RISC V, RISC-V architecture, RISCV 
RISC-V (pronounced "risk-five") is an open-source instruction set architecture (ISA) based on established reduced instruction set computing (RISC… 
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Related topics

Related topics

50 relations
128-bitAVX-512Advanced Vector ExtensionsAssembly language

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
RVTensor: A Light-Weight Neural Network Inference Framework Based on the RISC-V Architecture
The open-source instruction set architecture RISC-V has developed rapidly in recent years, and its combination mode of multiple… 
2019
2019
Acceleration of Lightweight Block Ciphers on Microprocessors
Cryptography is a key element to the development of secure communication in embedded environment such as within or between… 
2018
2018
Using Constraints for SystemC AMS Design and Verification
In this paper we discuss how constraints can be applied for the design and verification of mixed-signal virtual prototypes based… 
2018
2018
Hardware and protocols for authentication and secure computation
The Internet of Things has resulted in an exponential rise in the number of embedded electronic devices. This thesis deals with… 
2018
2018
The rise of RISC - [Opinion]
IN THE PAST DECADE, many technologists have adopted the mantra that software is eating the world. However, all of that software… 
2017
2017
The Deterministic Memory Abstraction and Supporting Cache Architecture for Multicore Real-Time Systems
Poor timing predictability of multicore processors has been a long-standing challenge in the real-time systems community. In this… 
2017
2017
An Efficient Runtime Validation Framework based on the Theory of Refinement
We introduce a new methodology based on refinement for testing the functional correctness of hardware and low-level software. Our… 
2014
2014
Micro-Policies A Framework for Verified, Hardware-Assisted Security Monitors
A wide range of low-level security policies can be expressed as rules on metadata tags and enforced using a combination of a… 
1991
1991
RISC 프로세서 승산기의 설계 ( The Design of a multiplier for RISC Processors )
1990
1990
RISC 프로세서 연산장치부의 설계 ( The Design of A RISC Processor`s ALU )
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