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RISC-V
Known as:
RISC V
, RISC-V architecture
, RISCV
RISC-V (pronounced "risk-five") is an open-source instruction set architecture (ISA) based on established reduced instruction set computing (RISC…
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Related topics
Related topics
50 relations
128-bit
AVX-512
Advanced Vector Extensions
Assembly language
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
Open-Source Validation Suite for RISC-V
M. Chupilko
,
A. Kamkin
,
Alexander Protsenko
International Workshop on Microprocessor Test and…
2019
Corpus ID: 212645869
In this paper, we propose a validation suite, applicable for different RISC-V designs. The suite can be considered as a stack of…
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2019
2019
RVTensor: A Light-Weight Neural Network Inference Framework Based on the RISC-V Architecture
Pengpeng Hou
,
Jiageng Yu
,
Yuxia Miao
,
Yang Tai
,
Y. Wu
,
Chen Zhao
BenchCouncil International Symposium
2019
Corpus ID: 219561086
The open-source instruction set architecture RISC-V has developed rapidly in recent years, and its combination mode of multiple…
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2018
2018
Hardware and protocols for authentication and secure computation
C. Juvekar
2018
Corpus ID: 58267379
The Internet of Things has resulted in an exponential rise in the number of embedded electronic devices. This thesis deals with…
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2018
2018
Using Constraints for SystemC AMS Design and Verification
Thilo Vörtler
,
K. Einwich
2018
Corpus ID: 140069994
In this paper we discuss how constraints can be applied for the design and verification of mixed-signal virtual prototypes based…
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2018
2018
A RISC-V ISA compatible processor IP for SoC
Suseela Budi
,
Pradeep Gupta
,
Kuruvilla Varghese
,
Amrutur Bharadwaj
International Symposium on Devices, Circuits and…
2018
Corpus ID: 49183246
The emergence of System-on-Chip technology has brought in opportunities in the form of reduced cycle time, superior performance…
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2017
2017
RTL Level Instruction Profiling for CPU Throttling to Reduce Wasted Dynamic Power
A. Owahid
,
E. John
International Conference on Computational Science…
2017
Corpus ID: 54456096
This paper identifies a set of instructions suitable for fine grained CPU throttling to reduce wasted dynamic power in RISCV…
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2017
2017
The Deterministic Memory Abstraction and Supporting Cache Architecture for Multicore Real-Time Systems
F. Farshchi
,
P. K. Valsan
,
R. Mancuso
,
H. Yun
2017
Corpus ID: 86593409
Poor timing predictability of multicore processors has been a long-standing challenge in the real-time systems community. In this…
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2014
2014
Micro-Policies A Framework for Verified, Hardware-Assisted Security Monitors
Arthur Azevedo de Amorim
,
B. Pierce
,
Antal Spector-Zabusky
,
A. Tolmach
2014
Corpus ID: 53994953
A wide range of low-level security policies can be expressed as rules on metadata tags and enforced using a combination of a…
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2008
2008
A RISC CPU IP core
P. Ye
,
Chaodong Ling
International Conference on Anti-counterfeiting…
2008
Corpus ID: 16004340
This article describes the hardware design of a RISC CPU IP core whose instructions are compatible with the Microchip PIC16C6X…
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1990
1990
RISC 프로세서 연산장치부의 설계 ( The Design of A RISC Processor`s ALU )
김대영
,
한충석
,
+4 authors
임인칠
1990
Corpus ID: 61947576
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