RISC-V

Known as: RISC V, RISC-V architecture, RISCV 
RISC-V (pronounced "risk-five") is an open-source instruction set architecture (ISA) based on established reduced instruction set computing (RISC… (More)
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Papers overview

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2017
2017
Endpoint devices for Internet-of-Things not only need to work under extremely tight power envelope of a few milliwatts, but also… (More)
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2017
2017
This paper presents a fast and accurate simulation methodology for performance, power, and energy evaluation in the hardware… (More)
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2016
2016
  • Jan Gray
  • IEEE 24th Annual International Symposium on Field…
  • 2016
GRVI is an FPGA-efficient RISC-V RV32I soft processor. Phalanx is a parallel processor and accelerator array framework. Groups of… (More)
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2016
2016
The final phase of CMOS technology scaling provides continued increases in already vast transistor counts, but only minimal… (More)
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2016
2016
This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching… (More)
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2015
2015
This work demonstrates a RISC-V vector microprocessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched… (More)
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Highly Cited
2014
Highly Cited
2014
RV32S implementations support a 32-bit virtual address space, divided into 4 KB pages. An RV32S virtual address is partitioned… (More)
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Highly Cited
2014
Highly Cited
2014
A 64-bit dual-core RISC-V processor with vector accelerators has been fabricated in a 45nm SOI process. This is the first dual… (More)
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2013
2013
Presents a collection of slides covering the following topics: RISC-V Instruction Set. 
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Highly Cited
1981
Highly Cited
1981
The Reduced Instruction Set Computer (RISC) Project investigates an alternatrve to the general trend toward computers wrth… (More)
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