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GRIP: A Graph Neural Network Accelerator Architecture
TLDR
GRIP splits GNN inference into a fixed set of edge- and vertex-centric execution phases that can be implemented in hardware, and supports severalGNN optimizations, including a novel optimization called vertex-tiling which increases the reuse of weight data. Expand
GRETA: HARDWARE OPTIMIZED GRAPH PROCESSING FOR GNNS
Graph Neural Networks (GNNs) are a type of deep neural network that can learn directly from irregular graphstructured data. However, GNN inference relies on sparse operations that are difficult toExpand
Design and Analysis of a Hardware CNN Accelerator
TLDR
A systolic array based architecture called ConvAU is designed and implemented to efficiently accelerate dense matrix multiplication operations in CNNs and finds that ConvAU gives a 200x improvement in TOPs/W when compared to a NVIDIA K80 GPU and a 1.9x improvement whenCompared to the TPU. Expand
Demo: Tethys -- An Energy Harvesting Networked Water Flow Sensor
We describe Tethys, an energy-harvesting wireless water flow sensor that can monitor water use at a per-fixture level with the intention of associating water use with specific individuals. Tethys wasExpand
Tethys: Collecting Sensor Data without Infrastracture or Trust
TLDR
The process of designing Tethys, a wireless water flow sensor that collects data at per-fixture granularity without dependence on existing infrastructure and trusted gateways is described, and initial findings from a deployment in undergraduate residential halls are presented. Expand
Falcon — A Flexible Architecture For Accelerating Cryptography
TLDR
Falcon provides the flexibility of software while reducing the energy consumption of cryptography by 5-60x compared to software, making it feasible for IoT applications to upgrade the ciphers they use after deployment without reducing their deployment lifetime or reducing the application workload. Expand
CESEL: Securing a Mote for 20 Years
TLDR
An initial design for what hardware security support such a mote should have is described, focusing on five hardware primitives: an atomic, unique counter, a random number generator based on physical entropy, additional instructions to accelerate symmetric ciphers, an elliptic curve accelerator, and support for modular polynomial multiplication used in post-quantum cryptographic signing algorithms. Expand
Shim Fetch and Decode Control Unit Program Counter Loop Ptr . 1 Iter . Count Loop Ptr . 2 Iter . Count Instruction
CESEL is a recently proposed cryptographic architecture that can accelerate a wide variety of ciphers, in contrast to most previous accelerator designs which focus on optimizing for a particularExpand