Skip to search form
Skip to main content
Skip to account menu
Semantic Scholar
Semantic Scholar's Logo
Search 225,098,306 papers from all fields of science
Search
Sign In
Create Free Account
R4000
Known as:
MIPS R4000
, R4400
The R4000 is a microprocessor developed by MIPS Computer Systems that implemented the MIPS III instruction set architecture (ISA). Officially…
Expand
Wikipedia
(opens in a new tab)
Create Alert
Alert
Related topics
Related topics
44 relations
64-bit computing
ARCS (computing)
Acer PICA
Advanced Computing Environment
Expand
Broader (1)
Advanced RISC Computing
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2000
2000
Interaction of JVM with x 86 , Sparc and MIPS
Sasikanth Avancha
,
D. Chakraborty
,
D. Gada
,
Tapan Kamdar
2000
Corpus ID: 15138070
A Java class is a perfect example of architecture independent code. A Java program can be compiled on a MIPS R4400 based Indy…
Expand
1998
1998
Reducing power consumption of dedicated processors through instruction set encoding
L. Benini
,
G. Micheli
,
A. Macii
,
E. Macii
,
M. Poncino
Proceedings of the 8th Great Lakes Symposium on…
1998
Corpus ID: 6131187
With the increased clock frequency of modern, high-performance processors (over 500 MHz, in some cases), limiting the power…
Expand
1997
1997
Feature based haptic rendering: architecture, protocol, and application
Juli Yamashita
,
C. Yi
,
Y. Fukui
International Conference on Computer Graphics and…
1997
Corpus ID: 28805623
3D I/O devices, long awaited in Computer Aided Design (CAD) systems, are finally available as force feedback devices such as…
Expand
1995
1995
Verification of a subtractive radix-2 square root algorithm and implementation
M. Leeser
,
J. O'Leary
Proceedings of ICCD '95 International Conference…
1995
Corpus ID: 38150804
Many modern microprocessors implement floating point square root hardware using subtractive algorithms. Such processors include…
Expand
1995
1995
Unroll-And-Jam Guided by A Linear-Algebra-Based Data-Reuse Model
Yiping Guan
1995
Corpus ID: 18798483
Because of the existence of a memory bottleneck in modern microprocessors, idle computational cycles in pipelined multiple…
Expand
1995
1995
A Parallel Accelerator for Using Synthetic Images in TV and Video Production
A. V. Sahiner
,
P. Lefloch
,
Y. Paker
1995
Corpus ID: 60714173
With the recent developments in digital media computers are used increasingly in TV production. Computer generated logos…
Expand
1994
1994
A 500 megabyte/second disk array
T. Ruwart
,
M. O'Keefe
1994
Corpus ID: 61108020
Applications at the Army High Performance Computing Research Center's (AHPCRC) Graphic and Visualization Laboratory (GVL) at the…
Expand
1994
1994
Tomographic image reconstruction and rendering with texture-mapping hardware
S. Azevedo
,
B. Cabral
,
Jim Foran
Optics & Photonics
1994
Corpus ID: 57627557
The image reconstruction problem, also known as the inverse Radon transform, for x-ray computed tomography (CT) is found in…
Expand
1993
1993
Specialized Caches To Improve Data Access Performance
B. Bray
1993
Corpus ID: 59732848
High performance processor organizations place large demands on the data memory hierarchy. The data bandwidth requirements of a…
Expand
1992
1992
Aerodynamic simulation on massively parallel systems
J. Haeuser
,
H. Simon
1992
Corpus ID: 15236147
This paper briefly addresses the computational requirements for the analysis of complete configurations of aircraft and…
Expand
By clicking accept or continuing to use the site, you agree to the terms outlined in our
Privacy Policy
(opens in a new tab)
,
Terms of Service
(opens in a new tab)
, and
Dataset License
(opens in a new tab)
ACCEPT & CONTINUE