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R3000

Known as: MIPS R3000, R3000A 
The R3000 is a full 32 bit RISC microprocessor chipset developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture… Expand
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Papers overview

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2009
2009
Geyser-1, a prototype MIPS R3000 CPU with fine grain runtime PG for major computational components in the execution stage is… Expand
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2008
2008
A fine-grain dynamic power gating is proposed for saving the leakage power in MIPS R3000 by sleep control and applied to a… Expand
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2003
2003
This paper relates our experience in designing from scratch a multi-threaded kernel for a MIPS R3000 on-chip multiprocessor. We… Expand
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2001
2001
This paper presents the speed and energy figures for an asynchronous implementation of a MIPS R3000 microprocessor. The design is… Expand
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1999
1999
Lab activity is fundamental for the real understanding of several computer science topics such as operating systems. We have… Expand
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Highly Cited
1997
Highly Cited
1997
The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0.6 /spl mu/m CMOS, we expect performance… Expand
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1996
1996
The project successfully demonstrated that dual lock-step comparison of commercial RISC processors is a viable fault-tolerant… Expand
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1995
1995
This paper presents a case study of worst case timing analysis for a RISC processor. The target machine consists of the R3000 CPU… Expand
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1994
1994
This document contains a speciication of the behavioural and real-time aspects of a typical MIPS R3000 RISC CPU. To increase… Expand
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1990
1990
SMART, a technique for providing predictable cache performance for real-time systems with priority-based preemptive scheduling… Expand
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