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Processor register

Known as: Register (computing), Processor registers, Memory register 
In computer architecture, a processor register is a quickly accessible location available to a digital processor's central processing unit (CPU… 
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32-bitAN/USQ-20Abstract machineAltiVec

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
High-Performance and Energy-Efficient Fault Diagnosis Using Effective Envelope Analysis and Denoising on a General-Purpose Graphics Processing Unit
This paper proposes an effective envelope analysis-based methodology for machinery condition monitoring and validates its… 
2010
2010
A 45nm 37.3GOPS/W heterogeneous multi-core SoC
We develop a heterogeneous multi-core SoC for applications, such as digital TV systems with IP networks (IP-TV) including image… 
2008
2008
Young drivers and their passengers: crash risk and group processes
The overall aim was to elucidate the effects of vehicle passengers on young drivers. This generated two specific aims and four… 
2005
2005
Digit-recurrence dividers with reduced logical depth
In this paper, we propose a class of division algorithms with the aim of reducing the delay of the selection of the quotient… 
Highly Cited
2000
Highly Cited
2000
3D map reconstruction from range data
We present techniques for building models of complex environments from range data gathered at multiple viewpoints. The challenges… 
Review
1993
Review
1993
Overview of the CHIP Compiler System
The MIPSpro compiler system consists of a set of components that enable you to create new 32-bit and 64-bit executable programs… 
1990
1990
Interconnect optimisation during data path allocation
  • L. Stok
  • Proceedings of the European Design Automation…
  • 1990
  • Corpus ID: 24861131
In previous research interconnection was optimised when the module allocation for the operations and the register allocation for… 
Highly Cited
1988
Highly Cited
1988
Allocation of multiport memories in data path synthesis
An algorithm to synthesize registers using multiport memories during data-path synthesis is presented. The proposed approach… 
1988
1988
On the hierarchical design of VLSI processor arrays
  • Lothar Thiele
  • ., IEEE International Symposium on Circuits and…
  • 1988
  • Corpus ID: 62687419
The author investigates systematic methods for the design of processor arrays. The proposed concept enables the efficient… 
Highly Cited
1969
Highly Cited
1969
Effects of Storage Contention on System Performance
This paper presents a mathematical model to measure the amount by which a computer's speed is reduced when it time-shares storage… 
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