• Publications
  • Influence
Efficient implementation of a BDD package
TLDR
This paper describes a package for manipulating Boolean functions based on the reduced, ordered, binary decision diagram (ROBDD) representation based on an efficient implementation of the if-then-else (ITE) operator. Expand
  • 1,369
  • 76
  • PDF
MIS: A Multiple-Level Logic Optimization System
TLDR
MIS is both an interactive and a batch-oriented multilevel logic synthesis and minimization system. Expand
  • 1,151
  • 42
Multiple-Valued Minimization for PLA Optimization
TLDR
This paper describes both a heuristic algorithm, Espresso-MV, and an exact algorithm for minimization of multiple-valued input, binary-valued output logic functions. Expand
  • 448
  • 33
Logic synthesis for vlsi design
TLDR
Logic synthesis is the automation of the logic design phase of scVLSI design; that is, choosing the specific gates and their interconnection to build a desired function. Expand
  • 302
  • 24
Dynamic variable ordering for ordered binary decision diagrams
TLDR
The ordered binary decision diagram (OBDD) has proven useful in many applications as an efficient data structure for representing and manipulating Boolean functions. Expand
  • 344
  • 16
Efficient Implementation Of Retiming
  • N. Shenoy, R. Rudell
  • Computer Science
  • IEEE/ACM International Conference on Computer…
  • 6 November 1994
TLDR
This paper addresses the implementation issues required to exploit the sparsity of circuit graphs to allow min-period retiming and constrained min-area retimings to be applied to circuits with as many as 10,000 combinational cells. Expand
  • 84
  • 7
Multi-level logic minimization using implicit don't cares
TLDR
We introduce the concept of R-minimality, which implies minimality with respect to cube reshaping, and demonstrate the crucial role played by this concept in multilevel minimization. Expand
  • 261
  • 6
  • PDF
Multiple-Valued Logic Minimization for PLA Synthesis
Abstract : Multiple-valued logic minimization is an important technique for reducing the area required by a Programmable Logic Array (PLA). This report describes both heuristic and exact algorithmsExpand
  • 96
  • 3
  • PDF
The Validity of Retiming Sequential Circuits
TLDR
We show that, while an accurate logic simulation may distinguish the retimed circuit from the original circuit, a conservative three-valued simulator cannot do so. Expand
  • 42
  • 2
  • PDF
Efficient implementation of retiming
TLDR
This paper addresses the implementation issues required to exploit the sparsity of circuit graphs to allow min-period retiming and constrained min-area retimming to be applied to circuits with as many as 10,000 combinational cells. Expand
  • 43
  • 2
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