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Processor array
Known as:
Array
, Processorarray
A processor array is like a storage array but contains and manages processing elements instead of storage elements. The processor array should have…
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Related topics
Related topics
8 relations
Backplane
Chassis
Computer cluster
Distributed computing
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Broader (1)
Concurrent computing
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2009
2009
A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array
Y. Saito
,
Toru Sano
,
Masaru Kato
,
Vasutan Tunbunheng
,
Yoshihiro Yasuda
,
H. Amano
International Conference on Engineering of…
2009
Corpus ID: 27585956
A power factor controller, a method of controlling power factor and a power converter employing either the controller or the…
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2007
2007
Modeling of Interconnection Networks in Massively Parallel Processor Architectures
A. Kupriyanov
,
Frank Hannig
,
+4 authors
S. Pillement
ARCS
2007
Corpus ID: 10488231
In this paper, we present a new concept for modeling of interconnection networks in the field of massively parallel processor…
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2007
2007
High performance processor array for image processing
Peter Foldesy
,
Á. Zarándy
,
C. Rekeczky
,
T. Roska
IEEE International Symposium on Circuits and…
2007
Corpus ID: 11509774
The ASIC implementation of a digital cellular visual microprocessor architecture is introduced. The processor array is…
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2004
2004
Sequential diagnosis of processor array systems
Jun Zhao
,
F. Meyer
,
N. Park
,
F. Lombardi
IEEE Transactions on Reliability
2004
Corpus ID: 1959668
We examine the diagnosis of processor array systems formed as two-dimensional arrays, with boundaries, and either four or eight…
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1996
1996
FPGA-based fine grain processor array design considerations
I. Erényi
,
I. Vassányi
Proceedings of Third International Conference on…
1996
Corpus ID: 61002261
Recent advances in FPGA technology offer a suitable environment for massively parallel, fine-grain array architectures. The paper…
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1993
1993
Transformational derivation of (parallel) programs using skeletons
E. Boiten
,
A. Geerling
,
H. Partsch
1993
Corpus ID: 15498858
We describe a framework for the derivation of programs for arbitrary (in particular, parallel) architectures, motivated by a…
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1993
1993
On the Design of Two-Level Pipelined Processor Arrays
D. Soudris
,
E. Kyriakis-Bitzaros
,
Vassilis Paliouras
,
M. Birbas
,
T. Stouraitis
,
C. Goutis
1993
Corpus ID: 61287922
This chapter addresses the design of two-level pipelined processor arrays. The parallelism of algorithms is exploited both in…
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1992
1992
Parallel volume rendering and data coherence on the Fujitsu AP1000
B. Corrie
,
P. Mackerras
1992
Corpus ID: 12908694
Many scienti c and engineering disciplines, through physical measurements or computational simulations, generate large scale…
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1990
1990
Implementation of ANN on RISC processor array
A. Hiraiwa
,
Masahiro Fujita
,
Shigeru Kurosu
,
Shigeru Arisawa
,
Makoto Inoue
[] Proceedings of the International Conference on…
1990
Corpus ID: 58744526
The authors present a mesh systolic array, GCN (giga connection), for a fast simulator of artificial neural networks (ANNs). The…
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1970
1970
COS/MOS parallel processor array
A. A. Alaspa
,
A. Dingwall
1970
Corpus ID: 62623636
A report on an LSI, COS/MOS parallel processor array posessing functional capabilities of an arithmetic unit 4-bit slice, will be…
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