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A 60 GHz sub-sampling PLL implemented in 40 nm CMOS is presented in this paper. The sub-sampling phase detector (SSPD) runs at 30… Expand The paper presents design optimization strategies and a comparison of the performance of SiGe HBT fundamental and push-push… Expand In this paper the power consumption and operating frequency of true single phase clock (TSPC) and extended true single phase… Expand We describe the application of subcarrier multiplexing (SCM) to enable broadband transmission beyond the modal bandwidth of… Expand A new ultra low voltage dynamic floating input D flip-flop (DFIDFF) is proposed for high speed prescaler circuit. Prescaler and… Expand The design of a dual modulus prescaler 32/33 in a 0.35 /spl mu/m CMOS technology is presented. The prescaler is a circuit… Expand The implementation of the two high-frequency building blocks for a low-phase-noise 1.8-GHz frequency-synthesizing PLL in a… Expand This paper describes a 2.7-V dual modulus (/spl divide/64/65, /spl divide/128/129) prescaler that operates up to 1.5 GHz with a… Expand A high-speed two-modulus prescaler for divide-by-4/5 select was successfully realized adopting a new circuit design that reduces… Expand