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A methodology has been proposed recently to predict error rates of cascade structures of blocks in Probabilistic CMOS (PCMOS). It… Expand In this paper we present a new model for characterization of probabilistic gates. While still not mainstream, probabilistic CMOS… Expand In this work, a novel approach using probabilistic CMOS (PCOMS) technology is used to reduce the energy consumption of a fuzzy… Expand The continuous miniaturization of CMOS feature sizes into the nanometer regime has increasingly caused problems due to noise… Expand The scaling trend of semiconductor devices has raised several issues such as energy consumption and heat dissipation, as well as… Expand Parameter variations, noise susceptibility, and increasing energy dissipation of cmos devices have been recognized as major… Expand Bayesian network (K.B. Korb and E. Nicholson, 2004) has received considerable attention in a great variety of research areas such… Expand Major impediments to technology scaling in the nanometer regime include power (or energy) dissipation and "erroneous" behavior… Expand Noise immunity and low-energy computing have become limiting factors in the semiconductor roadmap as transistor feature sizes… Expand
1 This work was supported in part by DARPA Seedling Contract #F30602-02-2-0124.