Skip to search form
Skip to main content
Skip to account menu
Semantic Scholar
Semantic Scholar's Logo
Search 227,741,318 papers from all fields of science
Search
Sign In
Create Free Account
Orthogonal instruction set
In computer engineering, an orthogonal instruction set is an instruction set architecture where all instruction types can use all addressing modes…
Expand
Wikipedia
(opens in a new tab)
Create Alert
Alert
Related topics
Related topics
19 relations
Accumulator (computing)
Addressing mode
Atmel AVR
Byte
Expand
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
Mac or Non-MAC: not a Problem
Libo Huang
,
Li Shen
,
Yashuai Lv
,
Zhiying Wang
,
Kui Dai
J. Circuits Syst. Comput.
2014
Corpus ID: 20648619
Multicore designs have become the dominant organization for future high performance microprocessors. Instead of increasing cache…
Expand
2013
2013
Green16: a frugal CPU architecture
Kevin A. Naudé
Research Conference of the South African…
2013
Corpus ID: 81384
A novel computer architecture called Green16 is presented. Green16 is designed with frugal innovation principles, and offers a…
Expand
Review
2007
Review
2007
The Multicomputer Toolbox Project Blais Working Note #0: Standard Sequential Mathematical Libraries: Promises and Pitfalls, Opportunities and Challenges
A. Lumsdaine
2007
Corpus ID: 16423654
The contribution of this paper is to lay a foundation for the development of next-generation standard sequential mathematical…
Expand
2004
2004
ODiN : A 32-Bit High Performance VLIW DSP for Software Defined Radio Applications
Seung-Eun Lee
,
Yong-Mu Jeong
2004
Corpus ID: 18099318
A very long instruction word (VLIW) digital signal processor (DSP), called ODiN, which could execute six instructions in a single…
Expand
Review
1999
Review
1999
Designing a NICE processor
B. Ulmann
Microprocessors and microsystems
1999
Corpus ID: 32189590
1986
1986
An 8MIPS CMOS digital signal processor
J. van Meerbergen
,
F. Welten
,
+6 authors
J. Wittek
IEEE International Solid-State Circuits…
1986
Corpus ID: 54121283
A 2μm digital signal processor with a 125ns instruction cycle will be described. It contains two 16b data buses, executes a 40b…
Expand
1986
1986
A 2-/spl mu/m CMOS 8-MIPS digital processor with parallel processing capability
F. Wijk
,
J. V. Meerbergen
,
+6 authors
J. Wittek
1986
Corpus ID: 63455043
A 2-/spl mu/m CMOS VLSI digital signal processor (DSP) family, the SP50, is described that is capable of eight million…
Expand
By clicking accept or continuing to use the site, you agree to the terms outlined in our
Privacy Policy
(opens in a new tab)
,
Terms of Service
(opens in a new tab)
, and
Dataset License
(opens in a new tab)
ACCEPT & CONTINUE