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Memory cell (binary)

Known as: 1 bit memory cell, Memory cell, DRAM cell 
The memory cell is the fundamental building block of computer memory. The memory cell is an electronic circuit that stores one bit of binary… 
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Related topics

Related topics

31 relations
Bubble memoryCARDboard Illustrative Aid to ComputationCPU cacheCombinational logic

Broader (2)

Digital electronicsElectronic engineering

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2013
Highly Cited
2013
A Thermally Stable and High-Performance 90-nm ${\rm Al}_{2}{\rm O}_{3}\backslash{\rm Cu}$-Based 1T1R CBRAM Cell
In this paper, we optimize the stack of a 90-nm CMOS-friendly W\Al<sub>2</sub>O<sub>3</sub>\Cu conductive-bridging random access… 
Highly Cited
2009
Highly Cited
2009
Printed Nonvolatile Memory for a Sheet-Type Communication System
By using state-of-the-art printing technologies and functional inks, we have demonstrated organic nonvolatile flexible random… 
Highly Cited
2006
Highly Cited
2006
An Ultra-Low-Power Memory With a Subthreshold Power Supply Voltage
A 512times13 bit ultra-low-power subthreshold memory is fabricated on a 130-nm process technology. The fabricated memory is fully… 
2003
2003
3D TFT-SONOS memory cell for ultra-high density file storage applications
For the first time, a scalable, low power, deep-submicron TFT-SONOS (Thin-Film Transistor Silicon-Oxide-Nitride-Oxide-Silicon… 
Highly Cited
2001
Highly Cited
2001
Data retention behavior of a SONOS type two-bit storage flash memory cell
  • W. TsaiN. Zous S. Gu
  • International Electron Devices Meeting. Technical…
  • 2001
  • Corpus ID: 34486471
Data retention loss mechanisms in a 2-bit SONOS type flash EEPROM cell with hot electron programming and hot hole erase are… 
Highly Cited
2000
Highly Cited
2000
Cosmic-ray soft error rate characterization of a standard 0.6-/spl mu/m CMOS process
Cosmic-ray soft errors from ground level to aircraft flight altitudes are caused mainly by neutrons. We derived an empirical… 
Highly Cited
1995
Highly Cited
1995
A multilevel-cell 32 Mb flash memory
A flash memory with multilevel cell significantly reduces the memory per-bit cost. A 32 Mb multilevel-cell (MLC) flash memory… 
Highly Cited
1987
Highly Cited
1987
An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM
A new single event upset (SEU) hardening concept, an LRAM cell, is demonstrated theoretically and experimentally. Decoupling… 
Highly Cited
1980
Highly Cited
1980
Testing Memories for Single-Cell Pattern-Sensitive Faults
The design of minimum-length test sequences for pattern sensitivity in random-access memory (RAM) arrays is examined. The single… 
1957
1957
Trapped-Flux Superconducting Memory
A memory cell based on trapped flux in superconductors has been built and tested. The cell is constructed entirely by vacuum… 
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