Skip to search form
Skip to main content
Skip to account menu
Semantic Scholar
Semantic Scholar's Logo
Search 231,756,933 papers from all fields of science
Search
Sign In
Create Free Account
Memory access pattern
Known as:
2D memory access pattern
, Gather-scatter memory access patterns
In computing, a memory access pattern or IO access patterns is the pattern with which a system or program reads and writes memory or secondary…
Expand
Wikipedia
(opens in a new tab)
Create Alert
Alert
Related topics
Related topics
31 relations
3D rendering
Cache (computing)
Cache pollution
Compute kernel
Expand
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
A GPU implementation of the harmonic sum algorithm
Karel Ad'amek
,
W. Armour
2018
Corpus ID: 119293674
Time-domain radio astronomy utilizes a harmonic sum algorithm as part of the Fourier domain periodicity search, this type of…
Expand
2016
2016
Functional Encryption from Secure Enclaves
S. Gorbunov
,
Dhinakaran Vinayagamurthy
IACR Cryptology ePrint Archive
2016
Corpus ID: 45112979
Functional encryption (FE) is an emerging paradigm for public-key cryptography that enables fine-grained access control over…
Expand
2013
2013
PseudoApp: Performance prediction for application migration to cloud
Byungchul Tak
,
Chunqiang Tang
,
Hai Huang
,
Long Wang
IFIP/IEEE Symposium on Integrated Network…
2013
Corpus ID: 14831188
To migrate an existing application to cloud, a user needs to estimate and compare the performance and resource consumption of the…
Expand
2011
2011
Static Memory Access Pattern Analysis on a Massively Parallel GPU
B. Jang
,
Dana Schaa
,
Perhaad Mistry
,
and David Kaeli
2011
Corpus ID: 15873460
The performance of data-parallel processing can be highly sensitive to any contention in memory. In contrast to multi-core CPUs…
Expand
2009
2009
MODA : A Memory Centric Performance Analysis Tool
J. Manzano
2009
Corpus ID: 17240735
From one processor generation to the next, the mismatch in processing speed vs. memory and network access speed is exacerbating…
Expand
2004
2004
High speed VLSI architecture for bit plane encoder of JPEG2000
A. Gupta
,
D. Taubman
,
S. Nooshabadi
The 47th Midwest Symposium on Circuits and…
2004
Corpus ID: 16799485
The bit plane coder is a part of the JPEG2000 embedded block coder. Its throughput plays a key role in deciding the overall…
Expand
2004
2004
Homeless and Home-based Lazy Release Consistency Protocols on Distributed Shared Memory
Byung-Hyun Yu
,
Zhiyi Huang
,
Stephen Cranefield
,
M. Purvis
Australasian Computer Science Conference
2004
Corpus ID: 1833359
This paper describes the comparison between homeless and home-based Lazy Release Consistency (LRC) protocols which are used to…
Expand
2004
2004
Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements
D. Stroobandt
,
H. Eeckhaut
,
H. Devos
,
M. Christiaens
,
F. Verdicchio
,
P. Schelkens
International Conference / Workshop on Embedded…
2004
Corpus ID: 17914750
Multimedia applications emerge on portable devices everywhere. These applications typically have a number of stringent…
Expand
2000
2000
3 D Seismic Modeling in a Message Passing Environment
S. Phadke
,
D. Bhardwaj
,
S. Yerneni
2000
Corpus ID: 17472627
In this paper we describe the MPI (Message Passing Interface) implementation of an algorithm for solving 3D acoustic wave…
Expand
1998
1998
Memory access pattern analysis
M. Brown
,
R. Jenevein
,
N. Ullah
Workload Characterization: Methodology and Case…
1998
Corpus ID: 60529646
A methodology for analyzing memory behavior has been developed for the purpose of evaluating memory system design. MPAT, a memory…
Expand
By clicking accept or continuing to use the site, you agree to the terms outlined in our
Privacy Policy
(opens in a new tab)
,
Terms of Service
(opens in a new tab)
, and
Dataset License
(opens in a new tab)
ACCEPT & CONTINUE