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Memory access pattern
Known as:
2D memory access pattern
, Gather-scatter memory access patterns
In computing, a memory access pattern or IO access patterns is the pattern with which a system or program reads and writes memory or secondary…
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31 relations
3D rendering
Cache (computing)
Cache pollution
Compute kernel
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
Efficient assembly for high order unstructured FEM meshes
P. Burovskiy
,
Paul Grigoras
,
S. Sherwin
,
W. Luk
International Conference on Field-Programmable…
2015
Corpus ID: 15717671
The Finite Element Method (FEM) is a common numerical technique used for solving Partial Differential Equations (PDEs) on complex…
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2013
2013
Exploring SIMD for Molecular Dynamics , Using Intel
J. Pennycook
,
C. Hughes
,
M. Smelyanskiy
,
S. Jarvis
2013
Corpus ID: 2909373
We analyse gather-scatter performance bottlenecks in molecular dynamics codes and the challenges that they pose for obtaining…
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2013
2013
A Library to Support the Development of Applications that Process Huge Matrices in External Memory
Jaqueline A. Silveira
,
S. V. G. Magalhães
,
M. Andrade
,
Vinicius S. Conceição
International Conference on Enterprise…
2013
Corpus ID: 23314404
This paper presents a new library, named TiledMatrix, to support the development of applications that process large matrices…
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2011
2011
Static Memory Access Pattern Analysis on a Massively Parallel GPU
B. Jang
,
Dana Schaa
,
Perhaad Mistry
,
and David Kaeli
2011
Corpus ID: 15873460
The performance of data-parallel processing can be highly sensitive to any contention in memory. In contrast to multi-core CPUs…
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2010
2010
QUAD - A Memory Access Pattern Analyser
S. A. Ostadzadeh
,
R. Meeuws
,
C. Galuzzi
,
K. Bertels
International Workshop on Applied Reconfigurable…
2010
Corpus ID: 18898697
In this paper, we present the Quantitative Usage Analysis of Data (QUAD) tool, a sophisticated memory access tracing tool that…
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2009
2009
MODA : A Memory Centric Performance Analysis Tool
J. Manzano
2009
Corpus ID: 17240735
From one processor generation to the next, the mismatch in processing speed vs. memory and network access speed is exacerbating…
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2004
2004
High speed VLSI architecture for bit plane encoder of JPEG2000
A. Gupta
,
D. Taubman
,
S. Nooshabadi
The 47th Midwest Symposium on Circuits and…
2004
Corpus ID: 16799485
The bit plane coder is a part of the JPEG2000 embedded block coder. Its throughput plays a key role in deciding the overall…
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2004
2004
Homeless and Home-based Lazy Release Consistency Protocols on Distributed Shared Memory
Byung-Hyun Yu
,
Zhiyi Huang
,
Stephen Cranefield
,
M. Purvis
Australasian Computer Science Conference
2004
Corpus ID: 1833359
This paper describes the comparison between homeless and home-based Lazy Release Consistency (LRC) protocols which are used to…
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2000
2000
3 D Seismic Modeling in a Message Passing Environment
S. Phadke
,
D. Bhardwaj
,
S. Yerneni
2000
Corpus ID: 17472627
In this paper we describe the MPI (Message Passing Interface) implementation of an algorithm for solving 3D acoustic wave…
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1998
1998
Memory access pattern analysis
M. Brown
,
R. Jenevein
,
N. Ullah
Workload Characterization: Methodology and Case…
1998
Corpus ID: 60529646
A methodology for analyzing memory behavior has been developed for the purpose of evaluating memory system design. MPAT, a memory…
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