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Reconfigurable computing: architectures and design methods
It is shown that reconfigurable computing designs are capable of achieving up to 500 times speedup and 70% energy savings over microprocessor implementations for specific applications.
Accuracy-Guaranteed Bit-Width Optimization
- Dong-U Lee, A. A. Gaffar, R. Cheung, O. Mencer, W. Luk, G. Constantinides
- Computer ScienceIEEE Transactions on Computer-Aided Design of…
- 1 October 2006
An automated static approach for optimizing bit widths of fixed-point feedforward designs with guaranteed accuracy, called MiniBit, is presented and is demonstrated with polynomial approximation, RGB-to-YCbCr conversion, matrix multiplication, B-splines, and discrete cosine transform placed and routed on a Xilinx Virtex-4 FPGA.
Wordlength optimization for linear digital signal processing
- G. Constantinides, P. Cheung, W. Luk
- Computer ScienceIEEE Trans. Comput. Aided Des. Integr. Circuits…
- 29 September 2003
This paper presents an approach to the wordlength allocation and optimization problem for linear digital signal processing systems implemented as custom parallel processing units. Two techniques are…
A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration
- Brahim Betkaoui, Yu Wang, David B. Thomas, W. Luk
- Computer ScienceIEEE 23rd International Conference on Application…
- 9 July 2012
This paper presents a reconfigurable hardware methodology for efficient parallel processing of large-scale graph exploration problems and achieves performance results that are superior to those of high performance multi-core systems in the recent literature for large graph instances.
A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation
- David B. Thomas, Lee W. Howes, W. Luk
- Computer ScienceSymposium on Field Programmable Gate Arrays
- 24 February 2009
For each platform, the most appropriate algorithm for generating each type of number is determined, then the peak generation rate and estimated power efficiency for each device are calculated.
NeMo: A Platform for Neural Modelling of Spiking Neurons Using GPUs
- A. Fidjeland, E. Roesch, M. Shanahan, W. Luk
- Computer Science, BiologyIEEE International Conference on Application…
- 7 July 2009
NeMo is presented, a platform for real-time spiking neural networks simulations which achieves high performance through the use of highly parallel commodity hardware in the form of graphics processing units (GPUs).
FP-BNN: Binarized neural network on FPGA
Gaussian random number generators
The algorithms underlying various GRNGs are described, their computational requirements are compared, and the quality of the random numbers are examined with emphasis on the behaviour in the tail region of the Gaussian probability density function.
F-CNN: An FPGA-based framework for training Convolutional Neural Networks
- Wenlai Zhao, H. Fu, Guangwen Yang
- Computer ScienceIEEE International Conference on Application…
- 6 July 2016
The proposed framework is based on reconfiguring a streaming datapath at runtime to cover the training cycle for the various layers in a CNN, and indicates that the proposed module design targeting Maxeler technology can achieve a performance of 62.06 GFLOPS for 32-bit floating-point arithmetic, outperforming existing accelerators.
Dynamic voltage scaling for commercial FPGAs
- G. C. Chow, L. S. M. Tsui, P. Leong, W. Luk, S. Wilton
- EngineeringProceedings. IEEE International Conference on…
- 11 December 2005
A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described and experiments using this technique on various circuits at different clock frequencies and temperatures are described to demonstrate its utility and robustness.