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Maze runner

Known as: Maze router 
Maze runner is a connection routing method that represents the entire routing space as a grid. Parts of this grid are blocked by components… 
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Related topics

Related topics

4 relations

Broader (2)

Electronic design automationElectronic engineering
Lee algorithmRouting

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2008
2008
Maze router based scheme for rotary clock router
Resonant rotary clocking is a novel clocking technology for low power, high frequency integrated circuits. Rotary clock… 
2005
2005
POMR: a power-aware interconnect optimization methodology
As VLSI technologies scale down, the average die size is expected to remain constant or to slightly increase with each generation… 
2005
2005
Congestion prediction in floorplanning
Routability optimization has become the major concern in floorplanning. In traditional floor planners, area minimization is an… 
Highly Cited
1999
Highly Cited
1999
Fast place and route approaches for fpgas
With recent advances in silicon device technology, a new branch of computer architecture, reconfigurable computing, has emerged… 
1992
1992
Plane parallel A* maze router and its application to FPGAs
  • M. Palczewski
  • [] Proceedings 29th ACM/IEEE Design Automation…
  • 1992
  • Corpus ID: 17149972
A plane-parallel maze-routing method for field programmable gate arrays is presented. It was demonstrated that a plane-parallel… 
1990
1990
Hybrid routing
  • Y. LinY. HsuF. Tsai
  • IEEE Trans. Comput. Aided Des. Integr. Circuits…
  • 1990
  • Corpus ID: 27728163
A general-purpose routing algorithm for very-large-scale integrated (VLSI) circuits and printed circuit board (PCB) designs is… 
1990
1990
A high-packing density module generator for bipolar analog LSIs
Efficient placement and routing algorithms are presented for the modules of a bipolar analog LSI. In the layout of an analog… 
Highly Cited
1988
Highly Cited
1988
LocusRoute: a parallel global router for standard cells
  • Jonathan Rose
  • 25th ACM/IEEE, Design Automation Conference…
  • 1988
  • Corpus ID: 15544293
A fast and easily parallelizable global routing algorithm for standard cells and its parallel implementation are presented… 
1987
1987
A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor
A new parallel-processing wire-routing algorithm is presented and implemented on a parallel processor. The two main features of… 
1983
1983
An Over-Cell Gate Array Channel Router
A gate array router that utilizes horizontal and vertical over-cell routing channels to increase cell density is described. Logic… 
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