• Publications
  • Influence
Post-CTS clock skew scheduling with limited delay buffering
  • Jianchao Lu, B. Taskin
  • Computer Science
  • 52nd IEEE International Midwest Symposium on…
  • 15 September 2009
tl;dr
Proposed post-clock-tree-synthesis (CTS) optimization method is delay buffering at the leaves of the clock tree to implement a limited version of clock skew scheduling. Expand
  • 12
  • 3
Timing Optimization Through Clock Skew Scheduling
tl;dr
This book details timing analysis and optimization techniques for circuits with level-sensitive memory elements and includes a delay insertion methodology that improves the efficiency of clock skew scheduling. Expand
  • 80
  • 2
Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking
  • B. Taskin, Bo Hong
  • Computer Science
  • IEEE Transactions on Very Large Scale Integration…
  • 1 December 2008
tl;dr
This paper describes a line-based, quantum-dot cellular automata (QCA) memory cell design that is synchronized by a dual-phase clocking scheme. Expand
  • 46
  • 1
Delay insertion method in clock skew scheduling
  • B. Taskin, I. Kourtev
  • Computer Science
  • IEEE Transactions on Computer-Aided Design of…
  • 3 April 2005
tl;dr
This paper describes a delay insertion method that improves the efficiency of clock skew scheduling by mitigating the limitations caused by reconvergent paths. Expand
  • 36
  • 1
From RTL to GDSII: An ASIC design course development using Synopsys® University Program
  • Jianchao Lu, B. Taskin
  • Engineering, Computer Science
  • IEEE International Conference on Microelectronic…
  • 5 June 2011
tl;dr
The development of an ASIC design course using the Synopsys University Program lectures, labs and tools is presented in this paper. Expand
  • 13
  • 1
Clock mesh synthesis with gated local trees and activity driven register clustering
tl;dr
This is the first work known in literature that encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. Expand
  • 13
  • 1
Delay Insertion Method in Clock Skew Scheduling
  • B. Taskin, I. Kourtev
  • Computer Science
  • IEEE Trans. Comput. Aided Des. Integr. Circuits…
  • 1 November 2006
tl;dr
This paper describes a delay insertion method that improves the efficiency of clock skew scheduling by mitigating the limitations caused by reconvergent paths. Expand
  • 10
  • 1
CROA: Design and Analysis of the Custom Rotary Oscillatory Array
tl;dr
In this paper, a novel design methodology called the CROA is proposed for the generation and distribution of rotary clocking. Expand
  • 16
  • 1
Steiner tree based rotary clock routing with bounded skew and capacitive load balancing
tl;dr
A novel rotary clock network routing method is proposed for the low-power resonant rotary clocking technology which guarantees: 1. The balanced capacitive load driven by each of the tapping points on the rotary rings, 2. Customized bounded clock skew among all the registers on chip, 3. A sub-optimally minimized total wirelength of the clock wire routes. Expand
  • 14
  • 1
Design Methodology for Voltage-Scaled Clock Distribution Networks
tl;dr
A low-voltage/swing clocking methodology is developed through both circuit and algorithmic innovations. Expand
  • 18
  • 1