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Low Pin Count

Known as: LPC, LPC bus, Low Pin Count bus 
The Low Pin Count bus, or LPC bus, is a computer bus used on IBM-compatible personal computers to connect low-bandwidth devices to the CPU, such as… 
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Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
Low frequency emphasis for lpc based coding in the frequency domain
2012
2012
Low pin count DfT technique for RFID ICs
The need of uniquely identifiable objects for multiple applications has given great attention to RFID ICs over the years. The… 
2012
2012
Safety of Low Pin Count Scan
Discloses only need two contactless smart card type IC pins are used for standard ATPG test. It may be used for a pin and a clock… 
2010
2010
Using a software exploit to image RAM on an embedded system
Review
2010
Review
2010
High performance, low pin count packaging
Advanced packaging conferences, technical articles, and editorials frequently focus on high pin count devices such as… 
2008
2008
High Test Quality in Low Pin Count Applications
We will show the real implementation of a very high test compression scheme for a 3 pin image sensor device. This new approach… 
2007
2007
Debug card and debug method
A debug card is inserted in the slot of a main board. The debug card comprises a programmable logic device, a PCI bus interface… 
2005
2005
Trusted computing and open source
2004
2004
Reaching detente in the design and material selection for Hi Rel WLCSP's
As WLCSP packaging technology travels the road to ubiquity a transition is unfolding. WLCSP designs and material selection… 
2002
2002
Reducing Synchronization Overhead in Test Data Compression Environments
Synchronization overhead between the core under test and the automatic test equipment is the main drawback of test data… 
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