Logical effort

Known as: Stage Effort, Branching Effort, Principle of logical effort 
The method of logical effort, a term coined by Ivan Sutherland and Bob Sproull in 1991, is a straightforward technique used to estimate delay in a… (More)
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Topic mentions per year

Topic mentions per year

1980-2017
05101519802017

Papers overview

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2009
2009
Designers often need to choose the gate sizes for logic circuit designs to estimate the delay of the circuit. Simulation and… (More)
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2008
2008
The method of ldquoLogical Effort Delay Modelrdquo allows designers to quickly estimate delay time and optimize logic paths. But… (More)
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2006
2006
The logical effort method is widely recognized as a pedagogical way allowing designers to quickly estimate and optimize single… (More)
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2005
2005
In this paper, modified logical effort (MLE) technique is proposed to provide delay estimation for CMOS gates. The model accounts… (More)
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2004
2004
A wide assortment of carry propagate adders offer varying areadelay tradeoff% Wiring and choice of circuit family also afiect the… (More)
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2004
2004
  • D. Harris
  • Conference Record of the Thirty-Eighth Asilomar…
  • 2004
Higher valency parallel prefix adders reduce the number of logic levels at the expense of greater fan-in at each level. This… (More)
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2004
2004
We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close to… (More)
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2003
2003
V 3 + W 0 3 # 0 6X W Y 6060(* Z / -,[ / # W 0 56 / -,[ / ' ) 0 \ / ". 0 [6 ( Q@ Z @ [". @6 ], A<>D ^_ @4 @ ` a>D W ` b6c =6 ], 3… (More)
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2002
2002
Application of logical effort on transistor-level analysis of different 64-bit adder topologies is presented. Logical effort… (More)
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2001
2001
This paper presents the transistor-level analysis of the 64-bit static carry-lookahead adder (CLA). The carry blocks were… (More)
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