The method of logical effort, a term coined by Ivan Sutherland and Bob Sproull in 1991, is a straightforward technique used to estimate delay in aâ€¦Â (More)

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2009

2009

- H. Hassan, I. M. Yassin, A. K. Halim, A. Zabidi, Z. A. Majid, H. Z. Abidin
- 2009 5th International Colloquium on Signalâ€¦
- 2009

Designers often need to choose the gate sizes for logic circuit designs to estimate the delay of the circuit. Simulation andâ€¦Â (More)

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2008

2008

- Chun-Hui Wu, Shun-Hua Lin, Herming Chiueh
- 2008 14th International Workshop on Thermalâ€¦
- 2008

The method of ldquoLogical Effort Delay Modelrdquo allows designers to quickly estimate delay time and optimize logic paths. Butâ€¦Â (More)

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2006

2006

- B. Lasbouygues, Sylvain Engels, Robin Wilson, Philippe Maurine, Nadine AzÃ©mard, Daniel Auvergne
- IEEE Transactions on Computer-Aided Design ofâ€¦
- 2006

The logical effort method is widely recognized as a pedagogical way allowing designers to quickly estimate and optimize singleâ€¦Â (More)

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2005

2005

- Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili
- IEEE Transactions on Computer-Aided Design ofâ€¦
- 2005

In this paper, modified logical effort (MLE) technique is proposed to provide delay estimation for CMOS gates. The model accountsâ€¦Â (More)

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2004

2004

- David Hanis, Ivan E. Sutherland, Harvey Mudd
- 2004

A wide assortment of carry propagate adders offer varying areadelay tradeoff% Wiring and choice of circuit family also afiect theâ€¦Â (More)

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2004

2004

- D. Harris
- Conference Record of the Thirty-Eighth Asilomarâ€¦
- 2004

Higher valency parallel prefix adders reduce the number of logic levels at the expense of greater fan-in at each level. Thisâ€¦Â (More)

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2004

2004

- Shrirang K. Karandikar, Sachin S. Sapatnekar
- IEEE/ACM International Conference on Computerâ€¦
- 2004

We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close toâ€¦Â (More)

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2003

2003

- Srividya Srinivasaraghavan, Wayne P. Burleson
- ISVLSI
- 2003

V 3 + W 0 3 # 0 6X W Y 6060(* Z / -,[ / # W 0 56 / -,[ / ' ) 0 \ / ". 0 [6 ( Q@ Z @ [". @6 ], A<>D ^_ @4 @ ` a>D W ` b6c =6 ], 3â€¦Â (More)

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2002

2002

- Hoang Q. Dao, Vojin G. Oklobdzija
- PATMOS
- 2002

Application of logical effort on transistor-level analysis of different 64-bit adder topologies is presented. Logical effortâ€¦Â (More)

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2001

2001

- H.Q. Dao, V. G. OklobdÅ¾ija
- Conference Record of Thirty-Fifth Asilomarâ€¦
- 2001

This paper presents the transistor-level analysis of the 64-bit static carry-lookahead adder (CLA). The carry blocks wereâ€¦Â (More)

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