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Logic redundancy

Known as: Redundancy 
Logic redundancy occurs in a digital gate network containing circuitry that does not affect the static logic function. There are several reasons why… 
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Related topics

Related topics

7 relations

Broader (3)

Boolean algebraDigital electronicsElectronic engineering
Iddq testingKarnaugh mapLogic gateRace condition

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
Piercing Logic Locking Keys through Redundancy Identification
The globalization of the IC supply chain witnesses the emergence of hardware attacks such as reverse engineering, hardware… 
2014
2014
A new binary arithmetic for finite-word-length linear controllers: MEMS applications
This paper addresses the problem of optimal hardware-realization of finite-word-length (FWL) linear controllers dedicated to MEMS… 
2011
2011
A 2.5mW 2Mb/s fully integrated impulse-FM-UWB transceiver in 0.18µm CMOS
This paper presents a fully integrated self-quenched super-regenerative impulse-FM-UWB transceiver architecture for wireless body… 
2010
2010
Is built-in logic redundancy ready for prime time?
With each new process generation, it becomes ever more challenging to maintain high yields of integrated circuits. Progressively… 
2008
2008
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy… 
Review
2005
Review
2005
Toward hardware-redundant, fault-tolerant logic for nanoelectronics
This article provides an overview of several logic redundancy schemes, including von Neumann's multiplexing logic, N-tuple… 
Highly Cited
2004
Highly Cited
2004
Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors
In this paper, various circuit and system level design challenges for nanometer-scale devices and single-electron transistors are… 
Highly Cited
1999
Highly Cited
1999
Radiation Test Results of the Virtex FPGA and ZBT SRAM for Space Based Reconfigurable Computing
A comprehensive Single Event Effects (SEE) characterization of advanced commercial technologies was conducted using the heavy-ion… 
1993
1993
Eliminating Redundant Training Data Using Unsupervised Clustering Techniques
Training data for supervised learning neural networks can be clustered such that the input/output pairs in each cluster are… 
1972
1972
Fault-Tolerant Computers Using ``Dotted Logic'' Redundancy Techniques
A new redundancy technique termed dotted logic is presented. Critical input errors are eliminated by joining together the output… 
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