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Logic redundancy
Known as:
Redundancy
Logic redundancy occurs in a digital gate network containing circuitry that does not affect the static logic function. There are several reasons why…
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Related topics
Related topics
7 relations
Broader (3)
Boolean algebra
Digital electronics
Electronic engineering
Iddq testing
Karnaugh map
Logic gate
Race condition
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
An Efficient,Effective and High Probability Clustering Based Algorithm For Feature Selection
Niharika Ankam
,
Pravallika Boddu
,
Vinay Chary Cholleti
2015
Corpus ID: 55164611
In machine learning and statistics, feature selection, also known as variable selection, attribute selection or variable subset…
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2013
2013
Fuzzy Features Selection Technique for Brain MR Images
Meenakshi R. B. Dubey
,
F. C. Morabito
,
+11 authors
Saeed Asadi
2013
Corpus ID: 390064
Brain tumors are the second leading cause of cancer deaths in human throughout the world. Therefore accurate diagnosis is…
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2013
2013
Mitigation of Single Event Upsets in the control logic of a charge equalizer for Li-ion batteries
F. Baronti
,
C. Bernardeschi
,
Luca Cassano
,
A. Domenici
,
R. Roncella
,
R. Saletti
Annual Conference of the IEEE Industrial…
2013
Corpus ID: 20705060
Lithium-ion batteries are increasingly being used in safety-critical applications, such as automotive, avionics and aerospace…
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2010
2010
Is built-in logic redundancy ready for prime time?
Chris Allsup
IEEE International Symposium on Quality…
2010
Corpus ID: 27984185
With each new process generation, it becomes ever more challenging to maintain high yields of integrated circuits. Progressively…
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2010
2010
Robust Fault Models Where Undetectable Faults Imply Logic Redundancy
I. Pomeranz
,
S. Reddy
IEEE Transactions on Very Large Scale Integration…
2010
Corpus ID: 28264637
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy…
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Highly Cited
2004
Highly Cited
2004
Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors
A. Schmid
,
Y. Leblebici
IEEE Transactions on Very Large Scale Integration…
2004
Corpus ID: 13590576
In this paper, various circuit and system level design challenges for nanometer-scale devices and single-electron transistors are…
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1999
1999
THE UPGRADED ELETTRA ACCESS CONTROL SYSTEM
A. Vascotto
,
D. Bulfone
,
+5 authors
M. Salvador
1999
Corpus ID: 110804082
The access control system of the ELETTRA accelerators must guarantee that access to the machine tunnels is allowed when safety…
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1993
1993
Eliminating Redundant Training Data Using Unsupervised Clustering Techniques
P. Gonsalves
,
M. Snorrason
,
A. Caglayan
1993
Corpus ID: 27676231
Training data for supervised learning neural networks can be clustered such that the input/output pairs in each cluster are…
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1990
1990
On the equivalence of fanout-point faults
A. Lioy
IEEE International Symposium on Circuits and…
1990
Corpus ID: 34117425
At the gate level, practical equivalence rules exist only for the faults on the inputs and output of a Boolean gate. It is shown…
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1972
1972
Fault-Tolerant Computers Using ``Dotted Logic'' Redundancy Techniques
H. Freeman
,
G. Metze
IEEE transactions on computers
1972
Corpus ID: 206619421
A new redundancy technique termed dotted logic is presented. Critical input errors are eliminated by joining together the output…
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