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Logic gate
Known as:
Universal logic gate
, Electronic logic gates
, Logical gate
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In electronics, a logic gate is an idealized or physical device implementing a Boolean function; that is, it performs a logical operation on one or…
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Related topics
Related topics
50 relations
AND-OR-Invert
Application-specific integrated circuit
Arithmetic logic unit
Asymmetric C-element
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2017
Highly Cited
2017
Design and Evaluation of an Efficient Schmitt Trigger-Based Hardened Latch in CNTFET Technology
Majid Moghaddam
,
M. H. Moaiyeri
,
M. Eshghi
IEEE transactions on device and materials…
2017
Corpus ID: 32431031
This paper presents a Schmitt trigger (ST) buffer using carbon nanotube FET (CNTFET) for reliable low-power applications…
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Highly Cited
2010
Highly Cited
2010
A Novel Anti-Collision Algorithm in RFID Systems for Identifying Passive Tags
S. Horng
,
Yuan-Hsin Chen
,
+5 authors
T. Terano
IEEE Transactions on Industrial Informatics
2010
Corpus ID: 16473955
Radio frequency identification has been developed and used in many applications in the real world. Due to the shared wireless…
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Highly Cited
2004
Highly Cited
2004
An approach to security and privacy of RFID system for supply chain
Xingxin Gao
,
Zhe Xiang
,
Hao Wang
,
Jun Shen
,
Jian Huang
,
Song Song
IEEE International Conference on E-Commerce…
2004
Corpus ID: 15916460
Radio frequency identification (RFID) is expected to become pervasive and ubiquitous, as it can be embedded into everyday items…
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Highly Cited
2003
Highly Cited
2003
Absence of Strong Gate Effects in Electrical Measurements on Phenylene-Based Conjugated Molecules
Jeong-O Lee
,
G. Lientschnig
,
+6 authors
C. Dekker
2003
Corpus ID: 15534581
The electronic transport characteristics of self-assembled monolayers of phenylene-based -conjugated molecules were measured in a…
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Highly Cited
2002
Highly Cited
2002
A Hardware-Software Real-Time Operating System Framework for SoCs
V. Mooney
,
D. Blough
IEEE Design & Test of Computers
2002
Corpus ID: 206458727
The /spl delta/ framework for RTOS-SoC codesign helps designers simultaneously build a SoC or platform-ASIC architecture and a…
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Highly Cited
1992
Highly Cited
1992
Certified timing verification and the transition delay of a logic circuit
S. Devadas
,
K. Keutzer
,
S. Malik
,
Albert R. Wang
[] Proceedings 29th ACM/IEEE Design Automation…
1992
Corpus ID: 14425007
The transition delay of a circuit is examined. It is shown that the transition delay of a circuit can differ from the floating…
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Highly Cited
1986
Highly Cited
1986
Elimination of process-dependent clock skew in CMOS VLSI
M. Shoji
1986
Corpus ID: 62734278
Delays of two clock signals propagating along their respective CMOS logic circuit paths can be matched against all processing…
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Highly Cited
1984
Highly Cited
1984
Design of testable logic circuits
R. Bennetts
1984
Corpus ID: 57043310
Highly Cited
1979
Highly Cited
1979
Bipolar transistor design for optimized power-delay logic circuits
D. Tang
,
P. Solomon
1979
Corpus ID: 62239089
This design optimization scheme provides a procedure for tailoring the impurity doping profile of the transistor so that the…
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Highly Cited
1976
Highly Cited
1976
Transition Count Testing of Combinational Logic Circuits
J. Hayes
IEEE transactions on computers
1976
Corpus ID: 206621034
Logic circuits are usually tested by applying a sequence of input patterns S to the circuit under test and comparing the observed…
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