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Logic gate
Known as:
Universal logic gate
, Electronic logic gates
, Logical gate
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In electronics, a logic gate is an idealized or physical device implementing a Boolean function; that is, it performs a logical operation on one or…
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Related topics
Related topics
50 relations
AND-OR-Invert
Application-specific integrated circuit
Arithmetic logic unit
Asymmetric C-element
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2009
Highly Cited
2009
Self-Routing Denial-of-Service Resistant Capabilities Using In-packet Bloom Filters
Christian Esteve Rothenberg
,
P. Jokela
,
P. Nikander
,
M. Sarela
,
J. Ylitalo
European Conference on Computer Network Defense
2009
Corpus ID: 15761064
In this paper, we propose and analyze an in-packet Bloom-filter-based source-routing architecture resistant to Distributed Denial…
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2007
2007
Ultra-low power subthreshold current-mode logic utilising PMOS load device
A. Tajalli
,
E. Vittoz
,
Y. Leblebici
,
E. J. Brauer
2007
Corpus ID: 30575165
A novel approach for implementing MOS current-mode logic (MCML) circuits that can operate with ultra low bias currents is…
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2007
2007
A new noise-tolerant dynamic logic circuit design
F. Frustaci
,
P. Corsonello
,
G. Cocorullo
Ph.D Research in Microelectronics and Electronics…
2007
Corpus ID: 28970455
This work proposes a new noise-tolerant dynamic circuit design. It has been extensively compared to previously published schemes…
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2004
2004
Understanding yield losses in logic circuits
D. Appello
,
A. Fudoli
,
Katia Giarda
,
V. Tancorre
,
Emil Gizdarski
,
B. Mathew
IEEE Design & Test of Computers
2004
Corpus ID: 10592721
Yield improvement requires understanding failures and identifying potential sources of yield loss. We focus on diagnosing random…
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1993
1993
Sequential test generation and synthesis for testability at the register-transfer and logic levels
A. Ghosh
,
S. Devadas
,
A. Newton
IEEE Trans. Comput. Aided Des. Integr. Circuits…
1993
Corpus ID: 45565062
The problem of test generation for nonscan sequential VLSI circuits is addressed. A novel method of test generation that…
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1992
1992
All Tests for a Fault are Not Eyually Valuable for Defect Detection
R. Kapur
,
Jaehong Park
,
Ray Mercer
Proceedings International Test Conference
1992
Corpus ID: 39102914
The standard approach to generating a test set for a logic circuit is to select a set of target fault,s and generate one test for…
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1992
1992
Spurious signals in digital CMOS VLSI circuits: a propagation analysis
F. Moll
,
A. Rubio
1992
Corpus ID: 61527501
Spurious signals may appear as a result of a variety of causes, such as hazards, crosstalk, and others. These signals may produce…
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1986
1986
Synapse: An Expert System for VLSI Design
P. Subrahmanyam
Computer
1986
Corpus ID: 18849365
V LSI design involves mapping a problem specification into mask V descriptions for circuit fabrication. This typically spans at…
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1967
1967
Analysis of Transmission Lines on Integrated-Circuit Chips
I. Ho
,
S. Mullick
1967
Corpus ID: 61939721
The availability of very fast semiconductor switching devices and the possibilities of large scale integration have increased the…
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1963
1963
Ternary Threshold Logic
W. Hanson
IEEE Transactions on Electronic Computers
1963
Corpus ID: 33590104
A new logical algebra, ternary threshold logic, is defined and developed. The system is shown to be capable of representing all…
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