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Logic gate
Known as:
Universal logic gate
, Electronic logic gates
, Logical gate
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In electronics, a logic gate is an idealized or physical device implementing a Boolean function; that is, it performs a logical operation on one or…
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Related topics
Related topics
50 relations
AND-OR-Invert
Application-specific integrated circuit
Arithmetic logic unit
Asymmetric C-element
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2009
Highly Cited
2009
Self-Routing Denial-of-Service Resistant Capabilities Using In-packet Bloom Filters
Christian Esteve Rothenberg
,
P. Jokela
,
P. Nikander
,
M. Sarela
,
J. Ylitalo
European Conference on Computer Network Defense
2009
Corpus ID: 15761064
In this paper, we propose and analyze an in-packet Bloom-filter-based source-routing architecture resistant to Distributed Denial…
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2007
2007
Ultra-low power subthreshold current-mode logic utilising PMOS load device
A. Tajalli
,
E. Vittoz
,
Y. Leblebici
,
E. J. Brauer
2007
Corpus ID: 30575165
A novel approach for implementing MOS current-mode logic (MCML) circuits that can operate with ultra low bias currents is…
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1993
1993
Sequential test generation and synthesis for testability at the register-transfer and logic levels
Abhijit Ghosh
,
S. Devadas
,
A. Newton
IEEE Trans. Comput. Aided Des. Integr. Circuits…
1993
Corpus ID: 45565062
The problem of test generation for nonscan sequential VLSI circuits is addressed. A novel method of test generation that…
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1992
1992
All Tests for a Fault are Not Eyually Valuable for Defect Detection
R. Kapur
,
Jaehong Park
,
Ray Mercer
Proceedings International Test Conference
1992
Corpus ID: 39102914
The standard approach to generating a test set for a logic circuit is to select a set of target fault,s and generate one test for…
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1987
1987
A Construction Method of High-Speed Decoders Using ROM's for Bose–Chaudhuri–Hocquenghem and Reed–Solomon Codes
H. Okano
,
H. Imai
IEEE transactions on computers
1987
Corpus ID: 37833982
In this paper, some efficient methods of solving equations over Galois field GF(2m) are proposed. Using these algorithms…
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1987
1987
A New Approach to the Design of Testable PLA's
S. Reddy
,
D. Ha
IEEE transactions on computers
1987
Corpus ID: 33730976
Programmable logic arrays (PLA's) are extensively used to realize area efficient combinational logic circuits. As the size of the…
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1978
1978
A Design of a Fast Cellular Associative Memory for Ordered Retrieval
C. Ramamoorthy
,
James L. Turner
,
B. Wah
IEEE transactions on computers
1978
Corpus ID: 13551389
In this paper, we design some simple schemes for a variety of searches, each of which may be performed in one complete memory…
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1975
1975
The Boolean Difference and Multiple Fault Analysis
Chia-Tai Ku
,
G. Masson
IEEE transactions on computers
1975
Corpus ID: 37728108
The Boolean difference is a well-known mathematical concept which has found significant application in the single fault analysis…
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1967
1967
Analysis of Transmission Lines on Integrated-Circuit Chips
I. Ho
,
S. Mullick
1967
Corpus ID: 61939721
The availability of very fast semiconductor switching devices and the possibilities of large scale integration have increased the…
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1963
1963
Ternary Threshold Logic
W. Hanson
IEEE Transactions on Electronic Computers
1963
Corpus ID: 33590104
A new logical algebra, ternary threshold logic, is defined and developed. The system is shown to be capable of representing all…
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