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List of Super NES enhancement chips
Known as:
DSP-1 (Super Nintendo)
, DSP-4 chip
, DSP-3 chip
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The list of Super NES enhancement chips demonstrates the overall design plan for the Super Nintendo Entertainment System, whereby the console's…
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29 relations
Application-specific integrated circuit
Arithmetic coding
Artificial intelligence
Bit plane
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
Analysis and Synthesis of Intelligent System for Electric Mode Control in Electric Arc Furnace
O. Lozynskyy
,
A. Lozynskyy
,
Y. Paranchuk
,
R. Paranchuk
,
Y. Marushchak
,
A. Malyar
2018
Corpus ID: 67281342
The hierarchical structure of the adaptive optimal control system for electric mode (EM) of the electric arc furnace is proposed…
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2009
2009
Hotspot detection and design recommendation using silicon calibrated CMP model
Colin Hui
,
Xian Bin Wang
,
+12 authors
T. Smith
Advanced Lithography
2009
Corpus ID: 120606064
Chemical Mechanical Polishing (CMP) has been used in the manufacturing process for copper (Cu) damascene process. It is well…
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2008
2008
Real-time simulation of photovoltaic arrays by growing neural gas controlled DC-DC converter
M. Cirrincione
,
M. C. Di Piazza
,
M. Pucci
,
G. Vitale
IEEE Power Electronics Specialists Conference
2008
Corpus ID: 42073136
This paper presents a real-time simulator of a photovoltaic array based on a Growing Neural Gas (GNG) controlled DC-DC buck…
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2008
2008
Mathematical modelling for keyhole surgery simulations: spleen capsule as an elastic membrabe:keyhole surgery simulations
P. Davies
,
F. Carter
,
D. Roxburgh
,
A. Cuschieri
2008
Corpus ID: 28732307
We show that the mechanical properties of the outer covering (or capsule) of pig spleen can be modelled as a nonlinear elastic…
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2008
2008
Implementation and usage of a freely available real-time operating system on an embedded robot controller
D. Hercog
,
A. Kapun
,
K. Jezernik
2008
Corpus ID: 14507447
Povzetek. V članku sta predstavljeni implementacija in uporaba p rosto dostopnega operacijskega sistema realnega čas na robotskem…
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1999
1999
Parallel Implementation of Multidimensional Transforms without Interprocessor Communication
F. Marino
,
E. Swartzlander
IEEE Trans. Computers
1999
Corpus ID: 18281244
Presents a modular algorithm which is suitable for computing a large class of multidimensional transforms in a general-purpose…
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1997
1997
Yield learning in integrated circuit package assembly
S. Balasubramaniam
,
A. Sarwar
,
D. Walker
1997
Corpus ID: 5321945
This paper describes a yield learning model for integrated circuit package assembly. The goal was to provide a management tool…
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1997
1997
Realization of a nonlinear digital filter on a DSP array processor
H. Kwan
,
E. Powers
,
E. Swartzlander
Proceedings IEEE International Conference on…
1997
Corpus ID: 35356726
This paper presents the performance evaluation of a fast third-order Volterra digital filtering algorithm mapped onto an AT&T DSP…
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1996
1996
Three-dimensional FFTs on a digital-signal parallel processor, with no interprocessor communication
H. Kwan
,
R.L. Nelson
,
E. Powers
,
E. Swartzlander
Conference Record of The Thirtieth Asilomar…
1996
Corpus ID: 24003579
This paper presents an efficient method of computing the three-dimensional DFT on the AT&T DSP-3 parallel processor. The method…
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1989
1989
A high performance reconfigurable parallel processing architecture
R. Shively
,
E. Morgan
,
T. Copley
,
A. Gorin
Proceedings of the ACM/IEEE Conference on…
1989
Corpus ID: 11917655
The architecture of the AT&T DSP-3 parallel processor is described. The DSP-3 design is modular and when implemented with 128…
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