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Adders are known to have being frequently used in VLSI designs. This work deals with the designing and implementing multipliers… Expand Vedic multiplier is an efficient system for faster result and optimized circuit design. Maintaining higher throughput in… Expand A fault tolerant adder implemented using Kogge-stone configuration can correct the error due to inherent redundancy in the carry… Expand The binary adder is the critical element in most digital circuit designs including digital signal processors (DSP) and… Expand The parallel scan is a basic tool that is used to parallelize algorithms which appear to have serial dependencies. The… Expand Multiplication is the basic building block for several DSP processors, Image processing and many other. Over the years the… Expand A methodology for energy-delay optimization of digital circuits is presented. This methodology is applied to minimizing the delay… Expand We describe the design of two three dimensional arithmetic units (a 3D adder and a 3D multiplier) that are implemented using… Expand We motivate the concept of comparing VLSI adders based on their energy-delay trade-offs and present a technique for estimating… Expand In this paper, we describe the design of radix-3 and radix-4 parallel prefix adders, that theoretically have logical depths of… Expand