Skip to search formSkip to main contentSkip to account menu

Kogge–Stone adder

Known as: Kogge-Stone, Kogge-Stone Adder 
The Kogge–Stone adder is a parallel prefix form carry look-ahead adder. Other parallel prefix adders include the Brent-Kung adder, the Han Carlson… 
Wikipedia (opens in a new tab)

Related topics

Related topics

5 relations
Adder (electronics)Carry (arithmetic)Carry-select adderCarry-skip adder

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
Design of Wallace Tree Multiplier Using Sparse Kogge-Stone and Brent–Kung Adders
In many digital signal processors and different applications, the massive role is played by the multiplier. In any VLSI design… 
2013
2013
Improved Fault Tolerant Sparse KOGGE Stone ADDER
A fault tolerant adder implemented using Kogge-stone configuration can correct the error due to inherent redundancy in the carry… 
2013
2013
Design and Characterization of Sparse Kogge Stone Parallel Prefix Adder Using FPGA
The binary adder is the critical element in most digital circuit designs including digital signal processors (DSP) and… 
2011
2011
A low-power methodology for configurable wide kogge-stone adders
We propose a methodology to reconfigure a wide Kogge- Stone (KS) adder that is typically used in multimedia applications in order… 
2011
2011
Asynchronous Hybrid Kogge-Stone Structure Carry Select Adder Based IEEE-754 Double-Precision Floating-Point Adder
In this paper, the design and implementation of a generic fast asynchronous Hybrid Kogge-Stone Structure Carry Select based Adder… 
2009
2009
Arithmetic unit design using 180nm TSV-based 3D stacking technology
We describe the design of two three dimensional arithmetic units (a 3D adder and a 3D multiplier) that are implemented using… 
2009
2009
Hybrid Prefix Adder Architecture for Minimizing the Power Delay Product
— Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and… 
2009
2009
A Novel Power Delay Optimized 32-bit Parallel Prefix Adder For High Speed Computing
Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and… 
2006
2006
A 5GHz+ 128-bit Binary Floating-Point Adder for the POWER6 Processor
A fast 128-bit end-around carry adder is designed and fabricated as part of the POWER6 floating-point unit in a 65nm SOI process… 
2005
2005
New Models of Prefix Adder Topologies
  • N. Burgess
  • J. VLSI Signal Process.
  • 2005
  • Corpus ID: 21992541
This paper introduces a variety of approaches for assessing logarithmic-depth parallel prefix adders: a delay model based on a… 
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)