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Kogge–Stone adder
Known as:
Kogge-Stone
, Kogge-Stone Adder
The Kogge–Stone adder is a parallel prefix form carry look-ahead adder. Other parallel prefix adders include the Brent-Kung adder, the Han Carlson…
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Related topics
Related topics
5 relations
Adder (electronics)
Carry (arithmetic)
Carry-select adder
Carry-skip adder
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Review
2019
Review
2019
A comprehensive review on the VLSI design performance of different Parallel Prefix Adders
S. Rakesh
,
K. S. V. Grace
Materials Today: Proceedings
2019
Corpus ID: 132604848
2017
2017
Design and performance analysis of multipliers using Kogge Stone Adder
A. Raju
,
Sudhir Kumar Sa
International Conference on Applied and…
2017
Corpus ID: 49352588
Adders are known to have being frequently used in VLSI designs. This work deals with the designing and implementing multipliers…
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2015
2015
Comparative study of performance vedic multiplier on the basis of adders used
Josmin Thomas
,
R. Pushpangadan
,
S. Jinesh
IEEE International WIE Conference on Electrical…
2015
Corpus ID: 8081135
Vedic multiplier is an efficient system for faster result and optimized circuit design. Maintaining higher throughput in…
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2013
2013
Improved Fault Tolerant Sparse KOGGE Stone ADDER
Mangesh B Kondalkar
,
A. Chavan
,
P. Narashimaraja
2013
Corpus ID: 16109187
A fault tolerant adder implemented using Kogge-stone configuration can correct the error due to inherent redundancy in the carry…
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2012
2012
Design of Braun Multiplier with Kogge Stone Adder & It's Implementation on FPGA
Javed Ashraf
2012
Corpus ID: 18309274
Multiplication is the basic building block for several DSP processors, Image processing and many other. Over the years the…
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Highly Cited
2012
Highly Cited
2012
Low Complexity Design of Ripple Carry and Brent–Kung Adders in QCA
V. Pudi
,
K. Sridharan
IEEE transactions on nanotechnology
2012
Corpus ID: 27958548
The design of adders on quantum dot cellular automata (QCA) has been of recent interest. While few designs exist, investigations…
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Highly Cited
2009
Highly Cited
2009
Energy–Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example
R. Zlatanovici
,
S. Kao
,
B. Nikolić
IEEE Journal of Solid-State Circuits
2009
Corpus ID: 13338442
A methodology for energy-delay optimization of digital circuits is presented. This methodology is applied to minimizing the delay…
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2009
2009
Arithmetic unit design using 180nm TSV-based 3D stacking technology
J. Ouyang
,
Guangyu Sun
,
+4 authors
M. Irwin
IEEE International Conference on 3D System…
2009
Corpus ID: 16524393
We describe the design of two three dimensional arithmetic units (a 3D adder and a 3D multiplier) that are implemented using…
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Highly Cited
2003
Highly Cited
2003
Energy-delay estimation technique for high-performance microprocessor VLSI adders
V. Oklobdzija
,
B. Zeydel
,
H. Dao
,
S. Mathew
,
R. Krishnamurthy
Proceedings 16th IEEE Symposium on Computer…
2003
Corpus ID: 331394
We motivate the concept of comparing VLSI adders based on their energy-delay trade-offs and present a technique for estimating…
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2000
2000
Higher radix Kogge-Stone parallel prefix adder architectures
Frank K. Gürkaynak
,
Y. Leblebici
,
L. Chaouat
,
P. J. McGuinness
IEEE International Symposium on Circuits and…
2000
Corpus ID: 3503945
In this paper, we describe the design of radix-3 and radix-4 parallel prefix adders, that theoretically have logical depths of…
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