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Kogge–Stone adder
Known as:
Kogge-Stone
, Kogge-Stone Adder
The Kogge–Stone adder is a parallel prefix form carry look-ahead adder. Other parallel prefix adders include the Brent-Kung adder, the Han Carlson…
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Related topics
Related topics
5 relations
Adder (electronics)
Carry (arithmetic)
Carry-select adder
Carry-skip adder
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
Design of Wallace Tree Multiplier Using Sparse Kogge-Stone and Brent–Kung Adders
M. L. Chowdary
,
A. Mallaiah
,
A. Lakshmi
Lecture Notes in Networks and Systems
2018
Corpus ID: 69841094
In many digital signal processors and different applications, the massive role is played by the multiplier. In any VLSI design…
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2013
2013
Improved Fault Tolerant Sparse KOGGE Stone ADDER
Mangesh B Kondalkar
,
A. Chavan
,
P. Narashimaraja
2013
Corpus ID: 16109187
A fault tolerant adder implemented using Kogge-stone configuration can correct the error due to inherent redundancy in the carry…
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2013
2013
Design and Characterization of Sparse Kogge Stone Parallel Prefix Adder Using FPGA
S. E.
,
Reenivasa
,
Oud
,
P. P.C
,
Raveen
,
Umar
2013
Corpus ID: 53518858
The binary adder is the critical element in most digital circuit designs including digital signal processors (DSP) and…
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2011
2011
A low-power methodology for configurable wide kogge-stone adders
Z. Moudallal
,
I. Issa
,
Mohammad M. Mansour
,
A. Chehab
,
A. Kayssi
International Conference on Energy Aware…
2011
Corpus ID: 33095532
We propose a methodology to reconfigure a wide Kogge- Stone (KS) adder that is typically used in multimedia applications in order…
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2011
2011
Asynchronous Hybrid Kogge-Stone Structure Carry Select Adder Based IEEE-754 Double-Precision Floating-Point Adder
Abhijith Kini
2011
Corpus ID: 8895666
In this paper, the design and implementation of a generic fast asynchronous Hybrid Kogge-Stone Structure Carry Select based Adder…
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2009
2009
Arithmetic unit design using 180nm TSV-based 3D stacking technology
J. Ouyang
,
Guangyu Sun
,
+4 authors
M. J. Irwin
IEEE International Conference on 3D System…
2009
Corpus ID: 16524393
We describe the design of two three dimensional arithmetic units (a 3D adder and a 3D multiplier) that are implemented using…
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2009
2009
Hybrid Prefix Adder Architecture for Minimizing the Power Delay Product
P. Ramanathan
,
P. Vanathi
2009
Corpus ID: 13879683
— Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and…
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2009
2009
A Novel Power Delay Optimized 32-bit Parallel Prefix Adder For High Speed Computing
P. Ramanathan
,
P. Vanathi
2009
Corpus ID: 10710215
Parallel Prefix addition is a technique for improving the speed of binary addition. Due to continuing integrating intensity and…
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2006
2006
A 5GHz+ 128-bit Binary Floating-Point Adder for the POWER6 Processor
X. Yu
,
Y. Chan
,
B. Curran
,
Eric M. Schwarz
,
Michael Kelly
,
Bruce M. Fleischer
Proceedings of the 32nd European Solid-State…
2006
Corpus ID: 14139400
A fast 128-bit end-around carry adder is designed and fabricated as part of the POWER6 floating-point unit in a 65nm SOI process…
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2005
2005
New Models of Prefix Adder Topologies
N. Burgess
J. VLSI Signal Process.
2005
Corpus ID: 21992541
This paper introduces a variety of approaches for assessing logarithmic-depth parallel prefix adders: a delay model based on a…
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