Skip to search formSkip to main contentSkip to account menu

Instructions per cycle

Known as: Instruction per cycle, IPC, Instructions Per Clock 
In computer architecture, instructions per cycle (IPC) is one aspect of a processor's performance: the average number of instructions executed for… 
Wikipedia (opens in a new tab)

Related topics

Related topics

28 relations
AMD Accelerated Processing UnitARM Cortex-A8Arithmetic logic unitAthlon

Broader (1)

Clock signal

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
A Generalized Model to Control the Throughput in a Processor for Real-Time Applications
In this paper we present a control theory approach to stabilize the throughput of threads for real-time applications on a… 
2007
2007
Register port complexity reduction in wide-issue processors with selective instruction execution
2005
2005
A Scalable GPU Architecture based on Dynamically Reconfigurable Embedded Processor
The increasing cost of ASIC has been driving designers to choose more flexible solutions, as new chip architectures should be… 
2004
2004
Cool-Fetch: a compiler-enabled IPC estimation based framework for energy reduction
With power consumption becoming an increasingly important factor, it is necessary to reevaluate traditional, power-intensive… 
2002
2002
Data Cache design considerations for the Itanium/sub /spl reg// 2 Processor
The second member in the Itanium Processor Family, the Itanium 2 processor, was designed to meet the challenge for high… 
1999
1999
DFT advances in the Motorola's MPC7400, a PowerPC/sup TM/ G4 microprocessor
Several advances have been made in the design for testability of the MPC7400, the first fourth generation PowerPC microprocessor… 
Review
1997
Review
1997
Constraints on parallelism beyond 10 instructions per cycle
The problem of extracting InstructionLevel Parallelism at levels of 10 instructionsper clock and higher is considered. Two… 
Highly Cited
1996
Highly Cited
1996
Thumb: reducing the cost of 32-bit RISC performance in portable and consumer applications
  • L. GoudgeS. Segars
  • COMPCON '96. Technologies for the Information…
  • 1996
  • Corpus ID: 206568018
This article discusses a RISC architectural innovation from ARM known as Thumb. High-end embedded control applications such as… 
1995
1995
Design of storage hierarchy in multithreaded architectures
Multithreaded execution models attempt to combine some aspects of dataflow-like execution with von Neumann model execution. Their… 
1990
1990
CMOS and ECL implementation of MIPS RISC architecture
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)