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Instruction-level parallelism

Known as: ILP, Instruction level parallelism 
Instruction-level parallelism (ILP) is a measure of how many of the instructions in a computer program can be executed simultaneously. There are two… 
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Related topics

Related topics

36 relations
Algorithmic efficiencyCentral processing unitCompile timeCompiler

Broader (1)

Parallel computing

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2004
2004
Investigating available instruction level parallelism for stack based machine architectures
Stack architectures have attracted much renewed research in recent years, due largely to the arrival of the JAVA programming… 
2003
2003
Software Carry-Save: A Case Study for Instruction-Level Parallelism
This paper is a practical study of the performance impact of avoiding data-dependencies at the algorithm level, when targeting… 
2001
2001
Instruction-level Parallelism
Instruction-level parallelism (ILP) is a set of processor and compiler design techniques that speed up program execution via the… 
2000
2000
Vliw processors: efficiently exploiting instruction level parallelism
This dissertation explores high-performance complexity-efficient processors foc u ing on VLIW processors. Complexity efficiency… 
2000
2000
Improved spill code generation for software pipelined loops
Software pipelining is a loop scheduling technique that extractsparallelism out of loops by overlapping the execution of… 
2000
2000
Quantifying instruction-level parallelism limits on an EPIC architecture
EPIC architectures rely heavily on state-of-the-art compiler technology to deliver optimal performance while keeping hardware… 
Highly Cited
1998
Highly Cited
1998
Clustered Instruction-Level Parallel Processors
VLIW, registers, clustering, compilers, EPIC, scheduling CPUs with a large amount of instruction-level parallelism must carry out… 
1998
1998
CoMPARE: A Simple Reconfigurable Processor Architecture Exploiting Instruction Level Parallelism
We propose CoMPARE, a Common Minimal Processor Architecture with Reconngurable Extension. It uses an LUT-based recon-gurable… 
1997
1997
Compilers for Instruction-Level Parallelism
Discovering and exploiting instruction level parallelism in code will be key to future increases in microprocessor performance… 
1993
1993
A comparision of superscalar and decoupled access/execute architectures
Even with a very accurate dynamic branch predictor, a superscalar processor must predict instruction fetch addresses no later… 
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