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- International Journal of Parallel Programming
The registers constraints are usually taken into account during the scheduling pass of an acyclic data dependence graph (DAG… (More)
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip… (More)
Trimaran is an integrated compilation and performance monitoring infrastructure. The architecture space that Trimaran covers is… (More)
Increasing demand for both greater parallelism and faster clocks dictate that future generation architectures will need to… (More)
Reconngurable coprocessors can exploit large degrees of instruction-level parallelism (ILP). In compiling sequential code for re… (More)
- ACM Trans. Comput. Syst.
To achieve high performance, contemporary computer systems rely on two forms of parallelism: instruction-level parallelism (ILP… (More)
Modern processors employ a large amount of hardware to dynamically detect parallelism in single-threaded programs and maintain… (More)
Current architectural trends in instruction-level parallelism (ILP) have significantly increased the computational power of… (More)
Growing interest in ambitious multiple-issue machines and heavilypipelined machines requires a careful examination of how much… (More)
Superscalar machines can issue several instructions per cycle. Superpipelined machines can issue only one instruction per cycle… (More)