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Instruction-level parallelism
Known as:
ILP
, Instruction level parallelism
Instruction-level parallelism (ILP) is a measure of how many of the instructions in a computer program can be executed simultaneously. There are two…
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Related topics
Related topics
36 relations
Algorithmic efficiency
Central processing unit
Compile time
Compiler
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Broader (1)
Parallel computing
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2004
2004
Investigating available instruction level parallelism for stack based machine architectures
Huibin Shi
,
C. Bailey
Euromicro Symposium on Digital System Design…
2004
Corpus ID: 14081633
Stack architectures have attracted much renewed research in recent years, due largely to the arrival of the JAVA programming…
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2003
2003
Software Carry-Save: A Case Study for Instruction-Level Parallelism
D. Defour
,
F. D. Dinechin
International Conference on Parallel…
2003
Corpus ID: 16480836
This paper is a practical study of the performance impact of avoiding data-dependencies at the algorithm level, when targeting…
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2001
2001
Instruction-level Parallelism
B. R. Rau
,
Joseph A. Fisher
2001
Corpus ID: 263268424
Instruction-level parallelism (ILP) is a set of processor and compiler design techniques that speed up program execution via the…
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2000
2000
Vliw processors: efficiently exploiting instruction level parallelism
M. Flynn
,
K. Rudd
2000
Corpus ID: 40307760
This dissertation explores high-performance complexity-efficient processors foc u ing on VLIW processors. Complexity efficiency…
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2000
2000
Improved spill code generation for software pipelined loops
J. Zalamea
,
J. Llosa
,
E. Ayguadé
,
M. Valero
ACM-SIGPLAN Symposium on Programming Language…
2000
Corpus ID: 11632589
Software pipelining is a loop scheduling technique that extractsparallelism out of loops by overlapping the execution of…
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2000
2000
Quantifying instruction-level parallelism limits on an EPIC architecture
Hsien-Hsin Lee
,
Youfeng Wu
,
G. Tyson
IEEE International Symposium on Performance…
2000
Corpus ID: 11629899
EPIC architectures rely heavily on state-of-the-art compiler technology to deliver optimal performance while keeping hardware…
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Highly Cited
1998
Highly Cited
1998
Clustered Instruction-Level Parallel Processors
P. Faraboschi
,
G. Desoli
,
+12 authors
Iloh Ehfrphv
1998
Corpus ID: 208911306
VLIW, registers, clustering, compilers, EPIC, scheduling CPUs with a large amount of instruction-level parallelism must carry out…
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1998
1998
CoMPARE: A Simple Reconfigurable Processor Architecture Exploiting Instruction Level Parallelism
S. Sawitzki
,
A. Gratz
,
R. Spallek
1998
Corpus ID: 18846116
We propose CoMPARE, a Common Minimal Processor Architecture with Reconngurable Extension. It uses an LUT-based recon-gurable…
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1997
1997
Compilers for Instruction-Level Parallelism
M. Schlansker
,
T. Conte
,
James C. Dehnert
,
K. Ebcioglu
,
J. Fang
,
C. L. Thompson
Computer
1997
Corpus ID: 37867209
Discovering and exploiting instruction level parallelism in code will be key to future increases in microprocessor performance…
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1993
1993
A comparision of superscalar and decoupled access/execute architectures
M. Farrens
,
Pius Ng
,
P. Nico
Proceedings of the 26th Annual International…
1993
Corpus ID: 3585445
Even with a very accurate dynamic branch predictor, a superscalar processor must predict instruction fetch addresses no later…
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