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Input/output base address
Known as:
Input Output Base Address
, PC I/O addressing
, PC input/output
In the x86 architecture, an input/output base address is the first address of a range of consecutive read/write addresses that a device uses on the…
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Related topics
Related topics
7 relations
Base address
Hardware register
IBM PC compatible
Intel 8237
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2012
2012
Static analysis of the worst-case memory performance for irregular codes with indirections
Diego Andrade
,
B. Fraguela
,
R. Doallo
TACO
2012
Corpus ID: 16304532
Real-time systems are subject to timing constraints, whose upper bound is given by the Worst-Case Execution Time (WCET). Cache…
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2010
2010
Device for filling and closing medicine containers of different types
U·克劳斯
,
S·欣普夫尔
,
U·迈尔
2010
Corpus ID: 196035916
The invention relates to a device (10) for filling and closing containers, in particular different types of pharmaceutical…
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2010
2010
Address-Independent Estimation of the Worst-Case Memory Performance
B. Fraguela
,
Diego Andrade
,
R. Doallo
IEEE Transactions on Industrial Informatics
2010
Corpus ID: 11649189
Real-time systems are subject to temporal constraints and require a schedulability analysis to ensure that task execution…
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2010
2010
Hierarchical data structure-based timing controller design for plasma display panels
Yeoul Na
,
Seokjoong Hwang
,
+4 authors
Taejin Kim
Proceedings of IEEE International Symposium on…
2010
Corpus ID: 5725241
In this paper, we propose a timing controller design to use a hierarchical structure of control signals for plasma display panels…
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2009
2009
High-Level Composite Type Reconstruction During Decompilation from Assembly Programs
K. Troshina
,
A. Chernov
2009
Corpus ID: 10074625
This paper presents a method for automatic reconstruction of high-level composite types during decompilation of C programs from…
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2008
2008
An Open-Source Modelica Library of Fluid Power Models
C. Paredis
2008
Corpus ID: 11798455
In this paper, a new open-source library of fluid power models is introduced. The intent of the library is to formally collect…
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2005
2005
How patterns in memory references affect the performance of hash functions in cache memories
B. Nootaert
,
Hans Vandierendonck
,
K. D. Bosschere
2005
Corpus ID: 16010755
Caches are sensitive to the presence of conflict misses, which occur when too many addresses in the working set are mapped to the…
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2003
2003
Hardware-based pointer data prefetcher
S. Lai
,
Shih-Lien Lu
Proceedings 21st International Conference on…
2003
Corpus ID: 46056179
Effective prefetching of data from a lower memory hierarchy to higher level is a helpful way to combat the increasing memory…
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1995
1995
Influence of cross-interferences on blocked loops: a case study with matrix-vector multiply
C. Fricker
,
O. Temam
,
W. Jalby
TOPL
1995
Corpus ID: 15111700
State-of-the art data locality optimizing algorithms are targeted for local memories rather than for cache memories. Recent work…
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1991
1991
Stack Tracing In A Statically Typed Language
Amer Diwan
1991
Corpus ID: 60632765
Statically-typed languages such as Modula-3 [Cardelli et al., 1989] provide many opportunities for compile-time garbage…
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