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High-level verification

Known as: High level verification 
High-level verification (HLV), or electronic system-level (ESL) verification, is the task to verify ESL designs at high abstraction level, i.e., it… 
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Related topics

Related topics

13 relations
Digital electronicsElectronic system-level design and verificationFormal methodsFormal verification

Broader (1)

Electronic design automation

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
Reasoning and algorithm selection augmented symbolic segmentation
In this paper an alternative method to symbolic segmentation is studied. Semantic segmentation being one of the most difficult… 
2016
2016
Python facilitates the rapid prototyping and hw/sw verification of processor centric SoCs for FPGAs
System Python (SysPy) is a public domain design tool using Python to facilitate all prototyping phases of processor-centric SoCs… 
2015
2015
High-level Synthesis Integrated Verification
It is widely known in the engineering community that more than 60% of the IC design project time is spent on verification. For… 
Review
2010
Review
2010
Canonical representations of high-level decision diagrams
In this paper we give a short overview of the decision diagrams, and define a special class of high-level decision diagrams (HLDD… 
2007
2007
From High-Level Verification to Real-Time Scheduling : A Property-Preserving Integration ?
In the design process of real-time systems, formal verification establishes global properties of high-level specifications while… 
2006
2006
A bottom-up approach to verification of hybrid model-based hierarchical controllers with application to underwater vehicles
We present a systematic method of verification for a hierarchical hybrid system which is developed using a bottom-up approach… 
2005
2005
Evaluation of Delay Queues for a Ravenscar Hardware Kernel
In this paper we present and evaluate four delay queues designed for application tailored Ravenscar hardware real time kernels… 
2001
2001
High-level verification of handwritten numeral strings
In this paper we discuss the use of high-level verification on handwritten numeral strings. First of all, we introduce the… 
2000
2000
A balanced approach to high-level verification: performance trade-offs in verifying large-scale multiprocessors
A single node of a modern scalable multiprocessor consists of several ASICs comprising tens of millions of gates. This level of… 
1987
1987
High level verification of (a)synchronous circuit descriptions
In the development of a silicon compiler, one has to choose if synchronous or selftimed systems should be generated. In the… 
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