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High-level verification
Known as:
High level verification
High-level verification (HLV), or electronic system-level (ESL) verification, is the task to verify ESL designs at high abstraction level, i.e., it…
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Related topics
Related topics
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Digital electronics
Electronic system-level design and verification
Formal methods
Formal verification
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Broader (1)
Electronic design automation
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Deterministic microcode machine generation
A. M'zah
,
B. Monsuez
,
H. Aboutaleb
International Conference on Data Science in…
2017
Corpus ID: 10264259
Microcode is a technique that is used to implement internal state machine sequencing in different type of controllers addressing…
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2016
2016
Reasoning and algorithm selection augmented symbolic segmentation
M. Lukac
,
Kamila Abdiyeva
,
M. Kameyama
Intelligent Systems with Applications
2016
Corpus ID: 4370082
In this paper an alternative method to symbolic segmentation is studied. Semantic segmentation being one of the most difficult…
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2015
2015
High-level Synthesis Integrated Verification
Michael F. Dossis
2015
Corpus ID: 54800787
It is widely known in the engineering community that more than 60% of the IC design project time is spent on verification. For…
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Review
2010
Review
2010
Canonical representations of high-level decision diagrams
Anton Karputkin
,
R. Ubar
,
J. Raik
,
M. Tombak
2010
Corpus ID: 52263885
In this paper we give a short overview of the decision diagrams, and define a special class of high-level decision diagrams (HLDD…
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2007
2007
From High-Level Verification to Real-Time Scheduling : A Property-Preserving Integration ?
Johannes Faber
,
Ingo Stierand
2007
Corpus ID: 8417830
In the design process of real-time systems, formal verification establishes global properties of high-level specifications while…
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2006
2006
A bottom-up approach to verification of hybrid model-based hierarchical controllers with application to underwater vehicles
M. O'Connor
,
S. Tangirala
,
Ratnesh Kumar
,
S. Bhattacharyya
,
M. Sznaier
,
L.E. Holloway
American Control Conference
2006
Corpus ID: 9892924
We present a systematic method of verification for a hierarchical hybrid system which is developed using a bottom-up approach…
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2005
2005
Evaluation of Delay Queues for a Ravenscar Hardware Kernel
Johan Furunäs
2005
Corpus ID: 9479941
In this paper we present and evaluate four delay queues designed for application tailored Ravenscar hardware real time kernels…
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2003
2003
A robust and scalable technique for the constraints solving problem in high-level verification
M. Iyer
Proceedings. 4th International Workshop on…
2003
Corpus ID: 18311567
Constraints solving is an important problem in a random simulation-based functional verification methodology. Constraints are…
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2001
2001
High-level verification of handwritten numeral strings
Luiz Oliveira
,
R. Sabourin
,
Flávio Bortolozzi
,
C. Suen
Proceedings XIV Brazilian Symposium on Computer…
2001
Corpus ID: 14635827
In this paper we discuss the use of high-level verification on handwritten numeral strings. First of all, we introduce the…
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2000
2000
A balanced approach to high-level verification: performance trade-offs in verifying large-scale multiprocessors
D. Abts
,
Mike Roberts
,
D. Lilja
Proceedings of the International Conference on…
2000
Corpus ID: 2290464
A single node of a modern scalable multiprocessor consists of several ASICs comprising tens of millions of gates. This level of…
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