Skip to search formSkip to main contentSkip to account menu

High-level verification

Known as: High level verification 
High-level verification (HLV), or electronic system-level (ESL) verification, is the task to verify ESL designs at high abstraction level, i.e., it… 
Wikipedia (opens in a new tab)

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Microcode is a technique that is used to implement internal state machine sequencing in different type of controllers addressing… 
2016
2016
In this paper an alternative method to symbolic segmentation is studied. Semantic segmentation being one of the most difficult… 
2015
2015
It is widely known in the engineering community that more than 60% of the IC design project time is spent on verification. For… 
Review
2010
Review
2010
In this paper we give a short overview of the decision diagrams, and define a special class of high-level decision diagrams (HLDD… 
2007
2007
In the design process of real-time systems, formal verification establishes global properties of high-level specifications while… 
2006
2006
We present a systematic method of verification for a hierarchical hybrid system which is developed using a bottom-up approach… 
2005
2005
In this paper we present and evaluate four delay queues designed for application tailored Ravenscar hardware real time kernels… 
2003
2003
  • M. Iyer
  • 2003
  • Corpus ID: 18311567
Constraints solving is an important problem in a random simulation-based functional verification methodology. Constraints are… 
2001
2001
In this paper we discuss the use of high-level verification on handwritten numeral strings. First of all, we introduce the… 
2000
2000
A single node of a modern scalable multiprocessor consists of several ASICs comprising tens of millions of gates. This level of…