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High-level verification
Known as:
High level verification
High-level verification (HLV), or electronic system-level (ESL) verification, is the task to verify ESL designs at high abstraction level, i.e., it…
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Related topics
Related topics
13 relations
Digital electronics
Electronic system-level design and verification
Formal methods
Formal verification
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Broader (1)
Electronic design automation
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Extensions of open core protocol and their high level verification using system verilog and UVM
G. Rani
,
Alekhya Pamarthy
,
M. Prakash
International Conference Inventive Communication…
2017
Corpus ID: 28374868
Today's scenario of semiconductor technology is a tremendous innovation, System on chip (SOC) design is of a great number of…
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2015
2015
Symbolic Segmentation Using Algorithm Selection
M. Lukac
,
Kamila Abdiyeva
,
M. Kameyama
arXiv.org
2015
Corpus ID: 3235084
In this paper we present an alternative approach to symbolic segmentation; instead of implementing a new method we approach…
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2015
2015
High-level Synthesis Integrated Verification
Michael F. Dossis
2015
Corpus ID: 54800787
It is widely known in the engineering community that more than 60% of the IC design project time is spent on verification. For…
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2013
2013
Verification and Error Correction on High-Level Decision Diagrams
Anton Karputkin
2013
Corpus ID: 67330766
This book explores the theory of High-Level Decision Diagrams in application to formal verification and design error correction…
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2007
2007
Us Ing A soC FUnCTIonAl VERIF ICATIon KIT To ImPRoVE PRodUCTIVITy, REdUCE RIsK, And InCREAsE QUAlITy
2007
Corpus ID: 14940657
2007
2007
From High-Level Verification to Real-Time Scheduling : A Property-Preserving Integration ?
Johannes Faber
,
Ingo Stierand
2007
Corpus ID: 8417830
In the design process of real-time systems, formal verification establishes global properties of high-level specifications while…
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2005
2005
Evaluation of Delay Queues for a Ravenscar Hardware Kernel
Johan Furunäs
2005
Corpus ID: 9479941
In this paper we present and evaluate four delay queues designed for application tailored Ravenscar hardware real time kernels…
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2003
2003
A robust and scalable technique for the constraints solving problem in high-level verification
M. Iyer
Proceedings. 4th International Workshop on…
2003
Corpus ID: 18311567
Constraints solving is an important problem in a random simulation-based functional verification methodology. Constraints are…
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2001
2001
High-level verification of handwritten numeral strings
Luiz Oliveira
,
R. Sabourin
,
Flávio Bortolozzi
,
C. Suen
Proceedings XIV Brazilian Symposium on Computer…
2001
Corpus ID: 14635827
In this paper we discuss the use of high-level verification on handwritten numeral strings. First of all, we introduce the…
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1987
1987
High level verification of (a)synchronous circuit descriptions
D. G. Jong
1987
Corpus ID: 38612478
In the development of a silicon compiler, one has to choose if synchronous or selftimed systems should be generated. In the…
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