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A method is presented in this paper for the design of high speed CMOS operational amplifiers (op-amp). The op-amp consists of an… Expand In this paper the fundamental tradeoff between speed, power, and accuracy for high-speed analog-to-digital converters (ADCs) is… Expand In high-speed CMOS clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a… Expand This paper describes a variable supply-voltage (VS) scheme. From an external supply, the VS scheme automatically generates… Expand The most important problems of designing a 12-bit high-speed CMOS D/A converter are studied. A modified current steering… Expand A CMOS implementation of a high-gain current mode operational amplifier (op amp) with a single-ended input and a differential… Expand It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process. This performance can be obtained… Expand The CMOS nonthreshold logic (NTL) is derived from its bipolar counterpart, which is the fastest bipolar logic, and takes the NOR… Expand A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m… Expand A 32-bit CMOS floating-point multiplier is described. The chip can perform 32-bit floating-point multiplication (based on the… Expand