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Gate dielectric
A gate dielectric is a dielectric used between the gate and substrate of a field-effect transistor. In state-of-the-art processes, the gate…
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Gate oxide
Hot-carrier injection
Quantum state
Semiconductor
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2010
2010
Fabrication and characterization of sol-gel-derived zinc oxide thin-film transistor
Y. Hwang
,
Seok-Jun Seo
,
B. Bae
2010
Corpus ID: 896747
Thin-film transistors (TFTs) with zinc oxide channel layers were fabricated through a simple and low-cost solution process…
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Highly Cited
2010
Highly Cited
2010
Bias-Stress Effect in Pentacene Organic Thin-Film Transistors
K. Ryu
IEEE Transactions on Electron Devices
2010
Corpus ID: 31812434
The effects of bias stress in integrated pentacene organic transistors are studied and modeled for different stress conditions…
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Highly Cited
2008
Highly Cited
2008
Si-Nanowire Based Gate-All-Around Nonvolatile SONOS Memory Cell
J. Fu
,
N. Singh
,
+10 authors
G. Baccarani
IEEE Electron Device Letters
2008
Corpus ID: 38319661
This letter presents a high-speed silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory cell in gate-all-around Si…
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2008
2008
Control of roughness at interfaces and the impact on charge mobility in all-polymer field-effect transistors
S. Chang
,
Ana B. Rodríguez
,
+6 authors
Yvonne Y. Deng
2008
Corpus ID: 96529190
The interfacial roughness at a buried dielectric–semiconductor interface in an all-polymer field-effect transistor (FET) is…
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2007
2007
Low-voltage organic thin film transistors with hydrophobic aluminum nitride film as gate insulator
H. Zan
,
Kuo-Hsi Yen
,
Pu-Kuan Liu
,
Kuo-Hsin Ku
,
Chien Hsun Chen
,
J. Hwang
2007
Corpus ID: 44012954
2006
2006
Leakage Biased pMOS Sleep Switch Dynamic Circuits
Zhiyu Liu
,
V. Kursun
IEEE Transactions on Circuits and Systems - II…
2006
Corpus ID: 15450688
In this brief, a low-overhead circuit technique is proposed to simultaneously reduce subthreshold and gate-oxide leakage currents…
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Highly Cited
2005
Highly Cited
2005
Germanium pMOSFETs with Schottky-barrier germanide S/D, high-/spl kappa/ gate dielectric and metal gate
Shiyang Zhu
,
Rui Li
,
+6 authors
D. Kwong
IEEE Electron Device Letters
2005
Corpus ID: 45875112
Schottky-barrier source/drain (S/D) germanium p-channel MOSFETs are demonstrated for the first time with HfAlO gate dielectric…
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Highly Cited
2004
Highly Cited
2004
Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode
Shiyang Zhu
,
H. Yu
,
+12 authors
D. Kwong
IEEE Electron Device Letters
2004
Corpus ID: 45415012
This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high…
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Highly Cited
2002
Highly Cited
2002
A sub-400/spl deg/C germanium MOSFET technology with high-/spl kappa/ dielectric and metal gate
C. O. Chui
,
Hyoungsub Kim
,
D. Chi
,
B. Triplett
,
P. McIntyre
,
K. Saraswat
Digest. International Electron Devices Meeting,
2002
Corpus ID: 21022685
A novel low thermal budget (/spl les/400/spl deg/C) germanium MOS process with high-/spl kappa/ gate dielectric and metal gate…
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Highly Cited
2001
Highly Cited
2001
High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE
S. Inaba
,
K. Okano
,
+25 authors
H. Ishiuchi
International Electron Devices Meeting. Technical…
2001
Corpus ID: 32942393
35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of…
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