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Gate count

In microprocessor design, gate count refers to the number of gates build with transistor and other electronic devices, that are needed to implement a… 
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Related topics

Related topics

7 relations
Block cipherESTREAMLogic gateMicroprocessor

Broader (1)

Semiconductor device fabrication

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering
The High Efficiency Video Coding (HEVC) in-loop filtering is designed to reduce coding artifacts caused by image transforms and… 
2013
2013
Area-Efficient Multimode Encoding Architecture for Long BCH Codes
This brief presents a new area-efficient multimode encoder for long Bose-Chaudhuri-Hocquenghen codes. In the proposed multimode… 
2011
2011
A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation
This paper deals with an FPGA implementation of a high performance FM modulator and demodulator for software defined radio (SDR… 
2010
2010
An Efficient VLSI Architecture for Nonbinary LDPC Decoders
Low-density parity-check (LDPC) codes constructed over the Galois field GF(q), which are also called nonbinary LDPC codes, are an… 
Highly Cited
2008
Highly Cited
2008
A Dynamic Optically Reconfigurable Gate Array—Perfect Emulation
This paper presents a perfect dynamic optically reconfigurable gate array (DORGA) architecture emulation using a holographic… 
2005
2005
Hardware implementation of large number multiplication by FFT with modular arithmetic
Modular multiplication (MM) for large integers is the foundation of most public-key cryptosystems, specifically RSA, El-Gamal and… 
2005
2005
Design of a High-Performance Scalable CDMA Router for On-Chip Switched Networks
Performance results and synthesized area overhead for a code division multiple access (CDMA) router intended for network-on-chip… 
Highly Cited
2003
Highly Cited
2003
Parallel 4/spl times/4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264
Transform coding has been widely used in video coding standards. In this paper, a hardware architecture for accelerating… 
2002
2002
Efficient ASIC implementation of a WCDMA Rake Receiver
This thesis is a study of a efficient ASIC implementation of a WCDMA Rake Receiver for the third generation mobile communication… 
1998
1998
Analysis of the XC6000 architecture for embedded system design
Novel FPGA architectures combined with new implementation methods influence the widespread area of embedded system design… 
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