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Floating-point unit
Known as:
Floating Point Unit
, Math coprocessor
, Floating-Point Processor
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A floating-point unit (FPU, colloquially a math coprocessor) is a part of a computer system specially designed to carry out operations on floating…
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Related topics
Related topics
50 relations
ARM architecture
AVR32
Apple A6
Arithmetic logic unit
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Broader (1)
Central processing unit
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
UPGMpp: a Software Library for Contextual Object Recognition
J. Ruiz-Sarmiento
,
C. Galindo
,
J. Gonzalez-Jimenez
2015
Corpus ID: 15322049
Universidad de Malaga. Campus de Excelencia Internacional Andalucia Tech. Spanish grant program FPU-MICINN 2010 and the Spanish…
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2011
2011
The POWER7 Binary Floating-Point Unit
M. Boersma
,
M. Kroener
,
Christophe Layer
,
Petra Leber
,
S. M. Müller
,
Kerstin Schelm
IEEE Symposium on Computer Arithmetic
2011
Corpus ID: 8068295
The binary Floating-Point Unit (FPU) of the POWER7 processor is a 5.5 cycle Fused Multiply-Add (FMA) design, fully compliant with…
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2010
2010
Design of Generic Floating Point Multiplier and Adder/Subtractor Units
L. S. A. Hamid
,
K. Shehata
,
H. El-Ghitani
,
M. Elsaid
12th International Conference on Computer…
2010
Corpus ID: 5729881
A high speed generic Floating Point Unit (FPU) consisting of a multiplier and adder/subtractor units is proposed. A novel…
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2008
2008
Characterization of Conflicts in Log-Based Transactional Memory (LogTM)
J. Gil
,
Manuel E. Acacio Sanchez
,
J. M. G. Carrasco
International Euromicro Conference on Parallel…
2008
Corpus ID: 11074452
The difficulty of multithreaded programming remains a major obstacle for programmers to fully exploit multicore chips…
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2007
2007
Binary Floating-Point Unit
S. D. Trong
,
M. Schmookler
,
E. Schwarz
,
M. Kroener
2007
Corpus ID: 15620247
The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an…
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2005
2005
Design and exploitation of a high-performance SIMD floating-point unit for Blue Gene/L
S. Chatterjee
,
Leonardo R. Bachega
,
+11 authors
Peng Wu
IBM Journal of Research and Development
2005
Corpus ID: 14480219
We describe the design of a dual-issue single-instruction, multiple-data-like (SIMD-like) extension of the IBM PowerPC® 440…
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2001
2001
1 GHz HAL SPARC64/sup R/ Dual Floating Point Unit with RAS features
A. Naini
,
Atul Dhablania
,
Warren James
,
Debjit Das Sarma
Proceedings 15th IEEE Symposium on Computer…
2001
Corpus ID: 29098624
An IEEE compliant, 1 GHz Sparc64-V Floating-Point Unit (FPU) with reliability-accessibility-serviceability (RAS) features and…
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Review
1999
Review
1999
A review of the state-ofthe-art of the methanol crossover in direct methanol fuel cells
A. Heinzel
,
V. M. Barragán
1999
Corpus ID: 55240057
Ž . Ž . Direct oxidation methanol fuel cells DMFCs are attractive for several applications, however, there are several barriers…
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1996
1996
The floating-point unit of the PowerPC 603e microprocessor
R. Jessani
,
Christopher Olson
IBM Journal of Research and Development
1996
Corpus ID: 31243598
The IBM PowerPC 603e floating-point unit (FPU) is an on-chip functional unit to support IEEE 754 standard single- and double…
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Highly Cited
1988
Highly Cited
1988
A 33 Mflops Floating Point Processor Using Redundant Binary Representation
H. Edamatsu
,
T. Taniguchi
,
T. Nishiyama
,
S. Kuninobu
IEEE International Solid-State Circuits…
1988
Corpus ID: 62225843
A 33MFLOPS single precision floating point processor that uses the redundant binary representation in a multiplier (FMUL) and a…
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