The POWER7 Binary Floating-Point Unit

  title={The POWER7 Binary Floating-Point Unit},
  author={Maarten Boersma and Michael Kroener and Christophe Layer and Petra Leber and Silvia M. M{\"u}ller and Kerstin Schelm},
  journal={2011 IEEE 20th Symposium on Computer Arithmetic},
The binary Floating-Point Unit (FPU) of the POWER7 processor is a 5.5 cycle Fused Multiply-Add (FMA) design, fully compliant with the IEEE 754-2008 standard. Unlike previous PowerPC designs, the POWER7 FPU merges the scalar and vector FPUs into a single unit executing three floating-point instruction sets: the single and double precision scalar set, the single precision VMX vector set, and the new single and double precision VSX vector and scalar set. Due to a compact buffer-free floor plan and… CONTINUE READING


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