The POWER7 Binary Floating-Point Unit

@article{Boersma2011ThePB,
  title={The POWER7 Binary Floating-Point Unit},
  author={Maarten Boersma and Michael Kroener and Christophe Layer and Petra Leber and Silvia M. M{\"u}ller and Kerstin Schelm},
  journal={2011 IEEE 20th Symposium on Computer Arithmetic},
  year={2011},
  pages={87-91}
}
The binary Floating-Point Unit (FPU) of the POWER7 processor is a 5.5 cycle Fused Multiply-Add (FMA) design, fully compliant with the IEEE 754-2008 standard. Unlike previous PowerPC designs, the POWER7 FPU merges the scalar and vector FPUs into a single unit executing three floating-point instruction sets: the single and double precision scalar set, the single precision VMX vector set, and the new single and double precision VSX vector and scalar set. Due to a compact buffer-free floor plan and… CONTINUE READING

Citations

Publications citing this paper.
Showing 1-5 of 5 extracted citations

References

Publications referenced by this paper.
Showing 1-9 of 9 references

4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers • 2006
View 13 Excerpts
Highly Influenced

AMD 3DNow! Technology and K6-2 Microprocessor

S. Oberman
Proc. Hot Chips • 1998
View 6 Excerpts
Highly Influenced

The complete Guide to MMX Technology”, McGraw-Hill/TAB Elec

D. Bistry
ISBN 0-07-006192-0, • 1997
View 6 Excerpts
Highly Influenced

The implementation of POWER7: A Highly Parallel and Scalable Multi-Core High-End Server Processor

D. Wendel
IEEE Intl. Solid-State Circ. Conf. Digest of Technical Papers, • 2010
View 2 Excerpts

IBM POWER6 accelerators: VMX and DFU

IBM Journal of Research and Development • 2007
View 8 Excerpts

IBM POWER6 microarchitecture

IBM Journal of Research and Development • 2007
View 1 Excerpt

P6 Binary Floating-Point Unit

18th IEEE Symposium on Computer Arithmetic (ARITH '07) • 2007
View 13 Excerpts

Similar Papers

Loading similar papers…