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Explicitly parallel instruction computing
Known as:
EPIC
, Epic architecture
, Intel EPIC
Explicitly parallel instruction computing (EPIC) is a term coined in 1997 by the HP–Intel alliance to describe a computing paradigm that researchers…
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Related topics
Related topics
30 relations
Backward compatibility
Burroughs large systems
CPU cache
Clock rate
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
: Pearl of Lahore Fort Complex , Lahore
Moti Masjid
,
Samina Zia Sheikh
2018
Corpus ID: 55170151
Mughal architecture is distinguished by domes, arches, vaulted roofs and various other features and has no parallel in adornment…
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2017
2017
Falcon : A Graph Manipulation Language for Distributed Heterogeneous Systems
Unnikrishnan Cheramangalath
2017
Corpus ID: 69312677
Graphs model relationships across real-world entities in web graphs, social network graphs, and road network graphs. Graph…
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2016
2016
Explicit Parallel Instruction Computing
P. Mathur
2016
Corpus ID: 36930166
: VLIW (Very Long Instruction Word) machines are highly parallel ILP (Instruction Level Parallelism) based architectures that…
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2007
2007
Leveraging Predicated Execution for Multimedia Processing
D. Ebner
,
F. Brandner
,
A. Krall
IEEE/ACM/IFIP Workshop on Embedded Systems for…
2007
Corpus ID: 18147634
Modern compression standards such as H.264, DivX, or VC-1 provide astonishing quality at the costs of steadily increasing…
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2003
2003
Adaptive explicitly parallel instruction computing for embedded systems
Dong Hai-tao
2003
Corpus ID: 58428317
Reconfigurable hardware offers the embedded systems the potential for significant performance improvements by providing support…
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2003
2003
A Comparative Analysis Between EPIC Statistic Instruction Scheduling and DTSVLIW Dynamic Instruction Scheduling
Sc Santana
,
A. D. Souza
,
P. Rounce
2003
Corpus ID: 8338361
To achieve performance, Explicitly Parallel Instruction Computing (EPIC) systems take the responsibility of extracting…
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2002
2002
Just-In-Time Java? Compilation for the Itanium® Processor
T. Shpeisman
,
Guei-Yuan Lueh
,
Ali-Reza Adl-Tabatabai
IEEE PACT
2002
Corpus ID: 249206186
2000
2000
Region-based Register Allocation for EPIC Architectures
Hansoo Kim
2000
Corpus ID: 28227733
Instruction-level parallelism (ILP) refers to a family of processor and compiler design techniques that speed up execution by…
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1999
1999
Assembly Language Programming Tools for the IA-64 Architecture
Ady Tal
1999
Corpus ID: 4463806
The IA-64 architecture, an implementation of Explicitly Parallel Instruction Computing (EPIC), enables the compiler to exercise…
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1985
1985
Supplement containing the missing pages needed to complete the Dru gu go rdzoṅ smad cha version of the Gesar epic
Tashi Tsering
1985
Corpus ID: 160202556