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Equivalent oxide thickness
Known as:
EOT
An Equivalent oxide thickness is a distance, usually given in nanometers (nm), which indicates how thick a silicon oxide film would need to be to…
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2 relations
Doping (semiconductor)
Semiconductor
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
0.2V adiabatic NC-FinFET with 0.6mA/µm ION and 0.1nA/µm IOFF
C. Hu
,
S. Salahuddin
,
Cheng-I Lin
,
Asif Khan
Device Research Conference
2015
Corpus ID: 24414090
We present for the first time a Negative Capacitance (NC) FinFET. Simulation shows 0.2V operation with 0.6mA/μm on-current and…
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2009
2009
Interface-Engineered High-Mobility High-$k$ /Ge pMOSFETs With 1-nm Equivalent Oxide Thickness
R. Xie
,
T. H. Phung
,
Wei He
,
Mingbin Yu
,
Chunxiang Zhu
IEEE Transactions on Electron Devices
2009
Corpus ID: 647329
High-k/germanium (Ge) interfaces are significantly improved through a new interface engineering scheme of using both effective…
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Highly Cited
2009
Highly Cited
2009
Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization
L. Ragnarsson
,
Zilan Li
,
+10 authors
T. Hoffmann
International Electron Devices Meeting
2009
Corpus ID: 30793094
A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO<sub>2</sub> based devices with a zero…
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2007
2007
Effects of High-$\kappa$ (HfO$_2$) Gate Dielectrics in Double-Gate and Cylindrical-Nanowire FETs Scaled to the Ultimate Technology Nodes
E. Gnani
,
S. Reggiani
,
M. Rudan
,
G. Baccarani
IEEE transactions on nanotechnology
2007
Corpus ID: 22278523
In this work we investigate the performance of double-gate and cylindrical nanowire FETs with high-kappa gate dielectrics at…
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Highly Cited
2005
Highly Cited
2005
Si interlayer passivation on germanium MOS capacitors with high-/spl kappa/ dielectric and metal gate
W. Bai
,
N. Lu
,
D. Kwong
IEEE Electron Device Letters
2005
Corpus ID: 37113314
We have demonstrated the advantages of silicon interlayer passivation on germanium MOS devices, with CVD HfO/sub 2/ as the high…
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Highly Cited
2004
Highly Cited
2004
Germanium p- & n-MOSFETs fabricated with novel surface passivation (plasma-PH/sub 3/ and thin AlN) and TaN/HfO/sub 2/ gate stack
S. Whang
,
S.J. Lee
,
+5 authors
D. Kwong
IEDM Technical Digest. IEEE International…
2004
Corpus ID: 24967330
Ge-MOS devices (EOT /spl sim/7.5 /spl Aring/, J/sub g/ /spl sim/ 10/sup -3/ A/cm/sup 2/) are fabricated on both n- & p-type Ge…
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Highly Cited
2003
Highly Cited
2003
Ge MOS characteristics with CVD HfO/sub 2/ gate dielectrics and TaN gate electrode
W. Bai
,
N. Lu
,
+6 authors
D. Antoniadis
Symposium on VLSI Technology. Digest of Technical…
2003
Corpus ID: 769787
In this paper, we report for the first time Ge MOS characteristics with ultra thin rapid thermal CVD HfO/sub 2/ gate dielectrics…
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2002
2002
Thermally stable CVD HfO/sub x/N/sub y/ advanced gate dielectrics with poly-Si gate electrode
C. Choi
,
S. Rhee
,
+5 authors
D. Kwong
Digest. International Electron Devices Meeting,
2002
Corpus ID: 24088881
In this paper, for the first time, we report high quality CVD hafnium oxynitride (HfOxNy) MOSFETs with conventional self-aligned…
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Highly Cited
2002
Highly Cited
2002
75 nm damascene metal gate and high-k integration for advanced CMOS devices
B. Guillaumot
,
X. Garros
,
+16 authors
S. Deleonibus
Digest. International Electron Devices Meeting,
2002
Corpus ID: 738647
An advanced CMOS process has been proposed which include key features: 75 nm gate length damascene metal gate, high-k dielectrics…
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1993
1993
Construction Contract Claims
R. Thomas
1993
Corpus ID: 166368852
Brief History of Construction Contracts and Case Law Choice of Contracts Tender and Acceptance Monitoring Delay and Disruption…
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