• Publications
  • Influence
Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
  • J. Tschanz, J. Kao, +4 authors V. De
  • Mathematics, Computer Science
  • IEEE International Solid-State Circuits…
  • 7 August 2002
Measurements on a 150 nm CMOS test chip show that on-chip bidirectional adaptive body biasing compensates effectively for die-to-die parameter variation to meet both frequency and leakageExpand
Measurement and modeling of self-heating in SOI nMOSFET's
Self-heating in SOI nMOSFET's is measured and modeled. Temperature rises in excess of 100 K are observed for SOI devices under static operating conditions. The measured temperature rise agrees wellExpand
Scaling of stack effect and its application for leakage reduction
A model that predicts the scaling nature of this leakage reduction effect is presented and use of stack effect for leakage reduction and other implications of this effect are discussed. Expand
A Simple Semiempirical Short-Channel MOSFET Current–Voltage Model Continuous Across All Regions of Operation and Employing Only Physical Parameters
A simple semiempirical model ID(VGS, VDS) for short-channel MOSFETs applicable in all regions of device operation is presented. The model is based on the so-calledExpand
Compact Virtual-Source Current–Voltage Model for Top- and Back-Gated Graphene Field-Effect Transistors
This paper presents a compact model for the current-voltage characteristics of graphene field-effect transistors (GFETs), which is based on an extension of the “virtual-source” model previouslyExpand
Design of Tunneling Field-Effect Transistors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions
Heterojunction tunneling field-effect transistors (HTFETs) that use strained-silicon/strained-germanium type-II staggered band alignment for band-to-band tunneling (BBT) injection are simulated usingExpand
Transistor Performance Scaling: The Role of Virtual Source Velocity and Its Mobility Dependence
An analytical model is used that relates MOSFET intrinsic delay to key technology parameters and a methodology for extracting those parameters from literature benchmark papers is presented and extrapolated to what is required for the performance scaling trend to continue. Expand
Transistor sizing issues and tool for multi-threshold CMOS technology
Avariable breakpoint switch level simulator that can rapidly calculatedelay in MTCMOS circuits as functions of design variablessuch as V{dd}, V{t}, and sleep transistor sizing is introduced. Expand
Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
This paper presents a sub-threshold leakage power prediction model that takes into account within-die threshold voltage variation and confirms that the mean error of the model to be 4%. Expand