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Dynamic voltage scaling

Known as: DVS, Voltage scaling, Undervolting 
Dynamic voltage scaling is a power management technique in computer architecture, where the voltage used in a component is increased or decreased… 
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Related topics

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ARM Cortex-MAccelerated Graphics PortAdvanced Configuration and Power InterfaceAndroid

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2009
Highly Cited
2009
A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS
In modern ICs, the trend of integrating more on-chip memories on a die has led SRAMs to account for a large fraction of total… 
Highly Cited
2007
Highly Cited
2007
Variation-Aware Adaptive Voltage Scaling System
Conventional voltage scaling systems require a delay margin to maintain a certain level of robustness across all possible device… 
Highly Cited
2007
Highly Cited
2007
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling… 
Highly Cited
2006
Highly Cited
2006
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison
  • M. AliotoG. Palumbo
  • IEEE Transactions on Very Large Scale Integration…
  • 2006
  • Corpus ID: 15372256
In this paper, some of the most practically interesting full adder topologies are analyzed in terms of their delay dependence on… 
Highly Cited
2005
Highly Cited
2005
A Feasibility Analysis of Power Awareness in Commodity-Based High-Performance Clusters
We present a feasibility study of a power-reduction scheme that reduces the thermal power of processors by lowering frequency and… 
Highly Cited
2005
Highly Cited
2005
Variability and energy awareness: a microarchitecture-level perspective
This paper proposes microarchitecture-level models for within die (WID) process and system parameter variability that can be… 
Highly Cited
2002
Highly Cited
2002
Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS… 
Highly Cited
1998
Highly Cited
1998
A low-power IDCT macrocell for MPEG2 MP@ML exploiting data distribution properties for minimal activity
This work describes the implementation of a low power IDCT chip targetted to medium and low bitrate applications. Our strategy… 
Highly Cited
1998
Highly Cited
1998
A 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme
This MPEG4 video codec implements essential functions in the MPEG4 committee draft. It consumes 60 mW at 30 MHz, 30% of the power… 
Highly Cited
1997
Highly Cited
1997
Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects
Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply… 
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