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Dynamic voltage scaling
Known as:
DVS
, Voltage scaling
, Undervolting
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Dynamic voltage scaling is a power management technique in computer architecture, where the voltage used in a component is increased or decreased…
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32 relations
ARM Cortex-M
Accelerated Graphics Port
Advanced Configuration and Power Interface
Android
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2009
Highly Cited
2009
A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS
M. Sinangil
,
N. Verma
,
A. Chandrakasan
IEEE Journal of Solid-State Circuits
2009
Corpus ID: 14948534
In modern ICs, the trend of integrating more on-chip memories on a die has led SRAMs to account for a large fraction of total…
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Highly Cited
2007
Highly Cited
2007
Variation-Aware Adaptive Voltage Scaling System
M. Elgebaly
,
M. Sachdev
IEEE Transactions on Very Large Scale Integration…
2007
Corpus ID: 12638702
Conventional voltage scaling systems require a delay margin to maintain a certain level of robustness across all possible device…
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Highly Cited
2007
Highly Cited
2007
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
N. Ahmed
,
M. Tehranipoor
,
Vinay B. Jayaram
44th ACM/IEEE Design Automation Conference
2007
Corpus ID: 207164169
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling…
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Highly Cited
2006
Highly Cited
2006
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison
M. Alioto
,
G. Palumbo
IEEE Transactions on Very Large Scale Integration…
2006
Corpus ID: 15372256
In this paper, some of the most practically interesting full adder topologies are analyzed in terms of their delay dependence on…
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Highly Cited
2005
Highly Cited
2005
A Feasibility Analysis of Power Awareness in Commodity-Based High-Performance Clusters
C. Hsu
,
Wu-chun Feng
IEEE International Conference on Cluster…
2005
Corpus ID: 14537295
We present a feasibility study of a power-reduction scheme that reduces the thermal power of processors by lowering frequency and…
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Highly Cited
2005
Highly Cited
2005
Variability and energy awareness: a microarchitecture-level perspective
Diana Marculescu
,
Emil Talpes
Proceedings - Design Automation Conference
2005
Corpus ID: 840213
This paper proposes microarchitecture-level models for within die (WID) process and system parameter variability that can be…
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Highly Cited
2002
Highly Cited
2002
Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
S. Narendra
,
V. De
,
S. Borkar
,
D. Antoniadis
,
A. Chandrakasan
International Symposium on Low Power Electronics…
2002
Corpus ID: 9811496
The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS…
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Highly Cited
1998
Highly Cited
1998
A low-power IDCT macrocell for MPEG2 MP@ML exploiting data distribution properties for minimal activity
T. Xanthopoulos
,
A. Chandrakasan
Symposium on VLSI Circuits. Digest of Technical…
1998
Corpus ID: 14383164
This work describes the implementation of a low power IDCT chip targetted to medium and low bitrate applications. Our strategy…
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Highly Cited
1998
Highly Cited
1998
A 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme
Masafumi Takahashi
,
M. Hamada
,
+15 authors
T. Furuyama
IEEE International Solid-State Circuits…
1998
Corpus ID: 31410962
This MPEG4 video codec implements essential functions in the MPEG4 committee draft. It consumes 60 mW at 30 MHz, 30% of the power…
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Highly Cited
1997
Highly Cited
1997
Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects
Kai Chen
,
C. Hu
,
Peng Fang
,
M. Lin
,
D. Wollesen
1997
Corpus ID: 18733041
Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply…
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