Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS

  title={Full-chip sub-threshold leakage power prediction model for sub-0.18 $\mu$m CMOS},
  author={S. Narendra and V. De and S. Borkar and D. Antoniadis and A. Chandrakasan},
  booktitle={ISLPED '02},
The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, control switching power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. With threshold voltage scaling sub-threshold leakage power is… Expand
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  • Engineering, Computer Science
  • 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)
  • 2007
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  • A. Keshavarzi, S. Ma, +5 authors V. De
  • ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581)
  • 2001
Examines the effectiveness of opportunistic use of reverse body bias (RBB) to reduce leakage power during active operation, burn-in, and standby in 0.18 /spl mu/m single-V/sub t/ and 0.13 /spl mu/mExpand
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  • V. De, S. Borkar
  • Engineering
  • Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477)
  • 1999
We discuss key barriers to continued scaling of supply voltage and technology for microprocessors to achieve low-power and high-performance. In particular, we focus on short-channel effects, deviceExpand
Threshold cancelling logic (TCL): a post-CMOS logic family scalable down to 0.02 /spl mu/m
  • I. Kohno, T. Sano, N. Katoh, K. Yano
  • Engineering
  • 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)
  • 2000
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  • Shih-Wei Sun, P. Tsui
  • Physics
  • Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94
  • 1994
A fundamental limit of CMOS supply-voltage (V/sub CC/) scaling has been investigated and quantified as a function of the statistical variation of MOSFET threshold-voltage (V/sub T/). Based on theExpand
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  • Materials Science
  • International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)
  • 2001
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