Dynamic timing verification

Dynamic timing verification refers to verifying that an ASIC design is fast enough to run without errors at the targeted clock rate. This is…

Papers overview

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2015

2015

Realistic dynamic timing verification for complex mixed signal hard macro's using UVM

Kunal PariharM. VenkateshRavikumar Patel
International Symposium on VLSI Design and Test
2015
Corpus ID: 216737

The paper addresses an attempt to perform dynamic timing simulations of complex mixed signal IP's. The targeted IP is a memory…

2004

2004

A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching

Y. EoSeongkyun ShinW. EisenstadtJ. Shim
IEEE Transactions on Computer-Aided Design of…
2004
Corpus ID: 4994924

In today's high-speed/high-density very large scale integrated (VLSI) circuit designs with coupled interconnect lines, signal…