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Dynamic-link library

Known as: Dynamic-Link Libraries, DLL, Declspec 
Dynamic-link library (or DLL) is Microsoft's implementation of the shared library concept in the Microsoft Windows and OS/2 operating systems. These… 
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Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
Dynamic Link Libraries
Dynamic Link Libraries DLL Fundamental DLL Theory How Imports Are Matched to Exports Implicit Linkage vs. Explicit Linkage… 
Highly Cited
2010
Highly Cited
2010
Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL
This paper presents the design of a time-to-digital converter (TDC) suitable for a 3.5-GHz all-digital phase-lock loop (PLL). The… 
2007
2007
Analysis of static and dynamic energy consumption in NUCA caches: initial results
NUCA caches are large L2 on-chip cache memories characterized by multi-bank partitioning and designed to hide wire delay effects… 
Highly Cited
2006
Highly Cited
2006
Intermediate-representation recovery from low-level code
The goal of our work is to create tools that an analyst can use to understand the workings of COTS components, plugins, mobile… 
2006
2006
Charge-pump reducing current mismatch in DLLs and PLLs
Conventional CMOS charge-pump circuits have some current mismatch problems. The current mismatch induces a phase offset which… 
2004
2004
On the design and management of heterogeneous networks: a predictability-based perspective
While great strides have been made in the design and deployment of commercial networks over the past two decades, relatively… 
2004
2004
Sensorless stand alone variable speed system for distributed generation
The following paper presents a variable speed stand alone power generating system. The system consists of a double fed induction… 
Highly Cited
2003
Highly Cited
2003
A low power CMOS Bluetooth transceiver with a digital offset canceling DLL-based GFSK demodulator
A 0.18/spl mu/m CMOS Bluetooth IC consumes 33mA in RX mode and 25mA in TX mode. The IC has a DLL-based GFSK demodulator with… 
2002
2002
A robust digital delay line architecture in a 0.13 /spl mu/m CMOS technology node for reduced design and process sensitivities
The combination of high operating frequencies and low-power requirements for DSP cores targeted towards mobile applications makes… 
2000
2000
A 1 GHz portable digital delay-locked loop with infinite phase capture ranges
Delay-locked loops (DLLs) are widely used to align signal phases in many high-speed microprocessors and memories. Phase-locked… 
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