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Dram Mass Unit

Known as: [fdr_us], Avoirdupois Dram, 1 [oz_av]/16 
The non-SI unit of mass equal to 1/16 Avoirdupois ounce or 1/256 Avoirdupois pound. One dram equals approximately 1.7718451953125 grams.
National Institutes of Health

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Apothecaries Dram Mass UnitClinical Data Interchange Standards Consortium Terminology

Papers overview

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2012
2012
Novel hybrid DRAM/MRAM design for reducing power of high performance mobile CPU
This paper presents novel DRAM/MRAM hybrid memory design that enables effective power reduction for high performance mobile CPU… 
2005
2005
Multi-mode embedded compression codec engine for power-aware video coding system
In a typical multi-chip handheld system for multi-media applications, external access, which is usually dominated by block-based… 
2004
2004
A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM
This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type… 
Highly Cited
2000
Highly Cited
2000
A 60 MHz 240 mW MPEG-4 video-phone LSI with 16 Mb embedded DRAM
A 240 mW single-chip MPEG-4 video-phone LSI with a 16 Mb embedded DRAM is fabricated in a 0.25 /spl mu/m CMOS, triple-well, quad… 
2000
2000
A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM
A 240-mW single-chip MPEG-4 videophone LSI with a 16-Mb embedded DRAM is fabricated utilizing a 0.25-/spl mu/m CMOS triple-well… 
1999
1999
A 1.6 GB/s DRAM with flexible mapping redundancy technique and additional refresh scheme
This DRAM features (1) interleaved operation of 16 dependent banks with 1.6 GB/s data rate, (2) flexible mapping redundancy which… 
Review
1998
Review
1998
Magneto-resistive IC memory limitations and architecture implications
  • R. Scheuerlein
  • Seventh Biennial IEEE International Nonvolatile…
  • 1998
  • Corpus ID: 109056105
Magnetoresistive (MR) elements offer an alternative approach to nonvolatile VLSI memory. The approach has unique aspects which… 
1996
1996
A multimedia 32 b RISC microprocessor with 16 Mb DRAM
This 32 b microprocessor with on-chip 2 MB DRAM is for multimedia applications that require a low-power embedded microprocessor… 
1993
1993
250 Mbyte/sec synchronous DRAM using a 3-stage-pipelined architecture
A 3.3 V 512 k/spl times/18/spl times/2 bank synchronous DRAM has been developed using a novel 3-stage-pipelined architecture. The… 
Highly Cited
1986
Highly Cited
1986
Investigation of MOS capacitors with thin ZrO2layers and various gate materials for advanced DRAM applications
Thin ZrO2layers were used to realize MOS capacitors with aluminum, polysilicon, and molybdenum gate electrodes. The layers, 300… 
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