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Don't-care term
Known as:
Don't-care (logic)
, Don't care
, Can't happen
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In digital logic, a don't-care term for a function is an input-sequence (a series of bits) for which the function output does not matter. An input…
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Related topics
Related topics
12 relations
And-inverter graph
Binary-coded decimal
Decision table
Flip-flop (electronics)
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2008
2008
Heuristic methods to use don’t cares in automated design of reversible and quantum logic circuits
Majid Mohammadi
,
M. Eshghi
Quantum Information Processing
2008
Corpus ID: 33683431
This paper introduces a broad concept of don’t cares in reversible and quantum logic circuits. Don’t cares are classified into…
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Highly Cited
2002
Highly Cited
2002
An automatic test pattern generator for minimizing switching activity during scan testing activity
Seongmoon Wang
,
S. Gupta
IEEE Trans. Comput. Aided Des. Integr. Circuits…
2002
Corpus ID: 39542852
An automatic test pattern generation (ATPG) technique is proposed that reduces switching activity during testing of sequential…
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Highly Cited
1995
Highly Cited
1995
Matching a Set of Strings with Variable Length don't Cares
G. Kucherov
,
M. Rusinowitch
Theoretical Computer Science
1995
Corpus ID: 3048836
Highly Cited
1989
Highly Cited
1989
Synthesis of delay fault testable combinational logic
K. Roy
,
J. Abraham
,
K. De
,
S. Lusky
IEEE International Conference on Computer-Aided…
1989
Corpus ID: 7689321
The synthesis of combinational logic which is robust delay fault testable is developed. In a circuit, any reconvergent fanout may…
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1989
1989
Redundancies and don't cares in sequential logic synthesis
S. Devadas
,
H. Ma
,
Richard Newton
Proceedings. 'Meeting the Tests of Time…
1989
Corpus ID: 11236105
The relationships between redundant logic and don't care conditions in combinational circuits are well known. Redundancies in a…
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1988
1988
Performance enhancements in BOLD using 'implications'
G. Hachtel
,
R. Jacoby
,
P. Moceyunas
,
C. Morrison
[] IEEE International Conference on Computer…
1988
Corpus ID: 1406015
Uses of implied network values or conditions in the context of multilevel logic synthesis are presented. The use of these…
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Highly Cited
1986
Highly Cited
1986
McBOOLE: A New Procedure for Exact Logic Minimization
M. Dagenais
,
V. Agarwal
,
N. Rumin
IEEE Transactions on Computer-Aided Design of…
1986
Corpus ID: 10077602
A new logic minimization algorithm is presented. It finds a minimal cover for a multiple-output boolean function expressed as a…
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1986
1986
Technology adaption in logic synthesis
W. Joyner
,
L. Trevillyan
,
D. Brand
,
T. A. Nix
,
S. C. Gundersen
Design Automation Conference
1986
Corpus ID: 28801188
Systems which synthesize logic implementations from specifications have moved, under the pressure of production requirements…
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Highly Cited
1970
Highly Cited
1970
Nonlinear Regression With Linear Constraints: An Extension of the Magnified Diagonal Method
R. Shrager
JACM
1970
Corpus ID: 19170775
A syntax-directed picture analysis system based on a formal picture description scheme is described. The system accepts a…
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1960
1960
Minimization over Boolean Trees
J. Roth
IBM Journal of Research and Development
1960
Corpus ID: 38201074
An algorithm is provided for what might be termea tne general problem ot logical design ot circuits with one output and no…
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