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Delay insensitive circuit
Known as:
Delay-insensitive
A delay insensitive circuit is a type of asynchronous circuit which performs a digital logic operation often within a computing processor chip…
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Related topics
Related topics
8 relations
Asynchronous circuit
Asynchronous system
Cache (computing)
Clock signal
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Broader (1)
Central processing unit
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Combined Biological and Chemical Mechanisms for Degradation of Insensitive Munitions in the Presence of Alternate Explosives
Kevin T. Finneran
,
Scott R. Drew
,
C. Arnett
2017
Corpus ID: 103268868
The Department of Defense (DoD) has developed next-generation explosives that have been updated with the insensitive munition (IM…
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2010
2010
Relaxed Quasi Delay-Insensitive Circuits
C. LaFrieda
2010
Corpus ID: 109122205
Deep submicron technologies are beginning to scale poorly with respect to both power and performance. It is well known that…
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2003
2003
An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication
Sunan Tugsinavisut
,
S. Jirayucharoensak
,
P. Beerel
Proceedings of the International Symposium on…
2003
Corpus ID: 21033759
This paper presents comprehensive energy-throughput comparisons of two well-known asynchronous design styles applied to a matrix…
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2003
2003
Evaluation of Australian RDX in PBXN-109
I. J. Lochert
,
Richard M. Dexter
,
B. L. Hamshere
2003
Corpus ID: 28611203
PBXN-109 is the explosive fill for a number of munitions including the Penguin ASM warhead which is being filled by ADI Limited…
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1999
1999
Verification of Scalable-Delay-Insensitive Asynchronous Circuits
A. Yamazaki
,
Hiroshi Ryu
,
T. Yoneda
1999
Corpus ID: 18255098
The Scalable-Delay-Insensitive (SDI) model is proposed for high-performance asynchronous system design. In this paper, we focus…
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1997
1997
Construction of an Operational Semantics for Di-algebra
J. T. Udding
1997
Corpus ID: 8124607
Numerous formalisms exist to specify delay-insensitive computations and their implementations. It is not always straightforward…
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1996
1996
Automated Synthesis of Delay-Insensitive Circuits
R. Sayle
1996
Corpus ID: 57356146
The technological trend towards VLSI circuits built from increasing numbers of transistors continues to challenge the ingenuity…
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1994
1994
Optimised synthesis of delay-insensitive circuits using time-sharing
H.-F. Li
,
S. Leung
,
P.-N. Lam
1994
Corpus ID: 62190482
A syntax-directed translation procedure for the synthesis of truly delay-insensitive circuits from graph theoretic specifications…
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1994
1994
Coding for delay-insensitive communication with partial synchronization
M. Blaum
,
Jehoshua Bruck
IEEE Transactions on Information Theory
1994
Corpus ID: 33852279
Assume that information is transmitted in parallel among many lines in such a way that an electrical transition represents a 1…
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1993
1993
Implementing a Stack as a Delay-insensitive Circuit
M. B. Josephs
,
J. T. Udding
Asynchronous Design Methodologies
1993
Corpus ID: 42276389
A case study in delay-insensitive circuit design is presented. A one bit wide stack is decomposed into an array of elements in a…
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