Delay insensitive circuit

Known as: Delay-insensitive 
A delay insensitive circuit is a type of asynchronous circuit which performs a digital logic operation often within a computing processor chip… (More)
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Topic mentions per year

1985-2017
010203019852017

Papers overview

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2008
2008
This paper presents a design methodology incorporating multi-threshold CMOS (MTCMOS) into delay-insensitive asynchronous circuits… (More)
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2006
2006
Slack matching is an optimization that determines the amount of buffering that must be added to each channel of a slack elastic… (More)
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2001
2001
The Quasi-Delay-Insensitive (QDI) model assumes that all the forks are isochronic. The isochronic-fork assumption requires… (More)
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1998
1998
We present the XDI Model for specifying delay-insensitive circuits, that is, reactive systems that correctly exchange signals… (More)
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1995
1995
Quasi-delay-insensitive (QDI) circuits are those whose correct operation does not depend on the delays of operators or wires… (More)
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Highly Cited
1991
Highly Cited
1991
A method for designing delay-insensitive circuits is presented based on a simple formalism. The communication behavior of a… (More)
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1990
1990
A novel process algebra is presented; algebraic expressions specify delay-insensitive circuits in terms of voltage-level… (More)
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Highly Cited
1989
Highly Cited
1989
Erik Brunvand* Carnegie Mellon University Programs written in a subset of occam are automatically translated into delay… (More)
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Highly Cited
1986
Highly Cited
1986
A method is described for compiling computations described as a set of communicating processes into VLSI circuits. The circuits… (More)
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Highly Cited
1986
Highly Cited
1986
Jan Tijmen Udding received the B.S. and M.S. degrees in mathematics, and the Ph.D. degree in computer science from the Eindhoven… (More)
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