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Delay insensitive circuit

Known as: Delay-insensitive 
A delay insensitive circuit is a type of asynchronous circuit which performs a digital logic operation often within a computing processor chip… 
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Related topics

Related topics

8 relations
Asynchronous circuitAsynchronous systemCache (computing)Clock signal

Broader (1)

Central processing unit

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2008
2008
Ultra-low power delay-insensitive circuit design
This paper presents a design methodology incorporating multi-threshold CMOS (MTCMOS) into delay-insensitive asynchronous circuits… 
2006
2006
GALS Networks on Chip: A New Solution for Asynchronous Delay-Insensitive Links
In this paper a cost effective solution for asynchronous delay-insensitive on-chip communication is proposed. Our solution is… 
2004
2004
Characterization of optimal resource allocation in cellular networks
Future wireless cellular systems are expected to carry a hybrid traffic including traditional voice transmissions delay-sensitive… 
Highly Cited
2003
Highly Cited
2003
Balanced self-checking asynchronous logic for smart card applications
2001
2001
Techniques for traffic engineering of multiservice, multipriority networks
We present techniques for traffic engineering in quality of service (QoS)-supported data networks and also illustrate the… 
1996
1996
Delay-Insensitive Circuits and Action Systems
The action systems formalism has been successfully used as a formal framework for reasoning about concurrent behaviour. Circuits… 
1996
1996
Automated Synthesis of Delay-Insensitive Circuits
The technological trend towards VLSI circuits built from increasing numbers of transistors continues to challenge the ingenuity… 
1993
1993
Implementing a Stack as a Delay-insensitive Circuit
A case study in delay-insensitive circuit design is presented. A one bit wide stack is decomposed into an array of elements in a… 
1991
1991
Parallel Computations and Delay-Insensitive Circuits
Delay-insensitive circuits are attractive implementations for parallel computations. A delay-insensitive circuit is a special… 
Highly Cited
1990
Highly Cited
1990
Using Partial-Order Semantics to Avoid the State Explosion Problem in Asynchronous Systems
We avoid state explosion in model checking of delay-insensitive VLSI systems by not using states. Systems are networks of… 
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