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Decimal64 floating-point format
Known as:
Decimal64
In computing, decimal64 is a decimal floating-point computer numbering format that occupies 8 bytes (64 bits) in computer memory.It is intended for…
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Related topics
Related topics
7 relations
Densely packed decimal
Double-precision floating-point format
ISO/IEC 10967
Machine epsilon
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Review
2014
Review
2014
Fast Radix-10 Multiplication Using Redundant BCD Codes
Álvaro Vázquez
,
E. Antelo
,
J. Bruguera
IEEE transactions on computers
2014
Corpus ID: 13708245
We present the algorithm and architecture of a BCD parallel multiplier that exploits some properties of two different redundant…
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2013
2013
Binary Integer Decimal-Based Floating-Point Multiplication
S. González-Navarro
,
C. Tsen
,
M. Schulte
IEEE transactions on computers
2013
Corpus ID: 30107369
This paper presents a multiplier that operates on binary integer decimal (BID) encoded decimal floating-point (DFP) numbers. It…
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2012
2012
On-line Decimal Adder with RBCD Representation
C. Garcia-Vega
,
S. González-Navarro
,
J. Villalba
,
E. Zapata
IEEE International Conference on Application…
2012
Corpus ID: 7096998
In this paper we present the design of an on-line adder dealing with two RBCD numbers. This basic element is intended to be be…
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2011
2011
A FPGA IEEE-754-2008 decimal64 Floating-Point adder/subtractor
Carlos Minchola
,
Martín Vázquez
,
G. Sutter
Southern Conference Programmable Logic
2011
Corpus ID: 10335756
This paper describes the FPGA implementation of a Decimal Floating Point (DFP) adder/subtractor. The design performs addition and…
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2009
2009
A FPGA IEEE-754-2008 Decimal64 Floating-Point Multiplier
Carlos Minchola
,
G. Sutter
International Conference on Reconfigurable…
2009
Corpus ID: 15028070
This paper describes the design and implementation of a hardware module to calculate the decimal floating-point DFP…
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2009
2009
A new decimal antilogarithmic converter
Dongdong Chen
,
Yu Zhang
,
D. Teng
,
K. Wahid
,
M. Lee
,
S. Ko
IEEE International Symposium on Circuits and…
2009
Corpus ID: 17044584
This paper presents a new design and implementation of a 32-bit decimal floating-point (DFP) antilogarithmic converter based on…
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2009
2009
Performance analysis of decimal floating-point libraries and its impact on decimal hardware and software solutions
Michael J. Anderson
,
C. Tsen
,
Liang-Kai Wang
,
Katherine Compton
,
M. Schulte
IEEE International Conference on Computer Design
2009
Corpus ID: 2767391
The IEEE Standards Committee recently approved the IEEE 754–2008 Standard for Floating-point Arithmetic, which includes…
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2009
2009
A 32-bit Decimal Floating-Point Logarithmic Converter
Dongdong Chen
,
Yu Zhang
,
Younhee Choi
,
M. Lee
,
S. Ko
IEEE Symposium on Computer Arithmetic
2009
Corpus ID: 14636943
This paper presents a new design and implementation of a 32-bit decimal floating-point (DFP) logarithmic converter based on the…
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2008
2008
A decimal fully parallel and pipelined floating point multiplier
R. Raafat
,
Amira M. Abdel-Majeed
,
+4 authors
H. Fahmy
Asilomar Conference on Signals, Systems and…
2008
Corpus ID: 9955793
Decimal arithmetic is important in several commercial applications including financial analysis, banking, tax calculation…
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2007
2007
A radix-10 SRT divider based on alternative BCD codings
Álvaro Vázquez
,
E. Antelo
,
P. Montuschi
ICCD
2007
Corpus ID: 18776946
In this paper we present the algorithm and architecture a radix-10 floating-point divider based on an SRT non-restoring digit-by…
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