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2013

2013

This paper presents a multiplier that operates on binary integer decimal (BID) encoded decimal floating-point (DFP) numbers. It… Expand

2012

2012

In this paper we present the design of an on-line adder dealing with two RBCD numbers. This basic element is intended to be be… Expand

2011

2011

This paper describes the FPGA implementation of a Decimal Floating Point (DFP) adder/subtractor. The design performs addition and… Expand

2010

2010

This paper presents the first hardware implementation of a fully parallel decimal floating-point fused-multiply-add unit… Expand

2009

2009

This paper describes the design and implementation of a hardware module to calculate the decimal floating-point DFP… Expand

2009

2009

This paper presents a new design and implementation of a 32-bit decimal floating-point (DFP) antilogarithmic converter based on… Expand

2009

2009

This paper presents a new design and implementation of a 32-bit decimal floating-point (DFP) logarithmic converter based on the… Expand

2009

2009

The IEEE Standards Committee recently approved the IEEE 754–2008 Standard for Floating-point Arithmetic, which includes… Expand

2008

2008

Decimal arithmetic is important in several commercial applications including financial analysis, banking, tax calculation… Expand

2007

2007

In this paper we present the algorithm and architecture a radix-10 floating-point divider based on an SRT non-restoring digit-by… Expand