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Double-precision floating-point format
Known as:
Double-precision
, Double precision floating point
, Double-precision floating-point
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Double-precision floating-point format is a computer number format that occupies 8 bytes (64 bits) in computer memory and represents a wide, dynamic…
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
Double precision floating point core in verilog
C. Aparna
,
M. Joseph
2016
Corpus ID: 64402995
A floating-point unit (FPU) is a math coprocessor, a part of a computer system specially designed to carry out operations on…
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2013
2013
A fully automated reconfigurable calculation engine dedicated to the real-time simulation of high switching frequency power electronic circuits
Tarek Ould-Bachir
,
C. Dufour
,
J. Bélanger
,
J. Mahseredjian
,
J. David
Mathematics and Computers in Simulation
2013
Corpus ID: 7818673
2011
2011
An efficient multiple precision floating-point multiplier
K. Manolopoulos
,
D. Reisis
,
V. Chouliaras
18th IEEE International Conference on Electronics…
2011
Corpus ID: 33524715
The current paper presents a multi-mode floating point multiplier operating efficiently with every precision format specified by…
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2011
2011
Godson-3B: A 1GHz 40W 8-core 128GFLOPS processor in 65nm CMOS
Weiwu Hu
,
Ru Wang
,
+5 authors
Xu Yang
IEEE International Solid-State Circuits…
2011
Corpus ID: 19621432
As the latest product of Godson processor series, the Godson-3B processor is an 8-core high-performance general-purpose processor…
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Highly Cited
2011
Highly Cited
2011
FPGA-based architecture for real time segmentation and denoising of HD video
M. Genovese
,
E. Napoli
Journal of Real-Time Image Processing
2011
Corpus ID: 402233
The identification of moving objects is a basic step in computer vision. The identification begins with the segmentation and is…
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Highly Cited
2009
Highly Cited
2009
SAPPORO: A way to turn your graphics cards into a GRAPE-6
E. Gaburov
,
S. Harfst
,
S. Zwart
arXiv.org
2009
Corpus ID: 10499579
Highly Cited
1998
Highly Cited
1998
Comparison of Single- and Dual-Pass Multiply-Add Fused Floating-Point Units
R. Jessani
,
M. Putrino
IEEE Trans. Computers
1998
Corpus ID: 39564895
Low power, low cost, and high performance factors dictate the design of many microprocessors targeted to the low power computing…
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Highly Cited
1995
Highly Cited
1995
167 MHz radix-4 floating point multiplier
R. Yu
,
G. Zyner
Proceedings of the 12th Symposium on Computer…
1995
Corpus ID: 38061019
An IEEE floating point multiplier with partial support for subnormal operands and results is presented. Radix-4 or modified Booth…
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Highly Cited
1993
Highly Cited
1993
A Recursive Carry-Lookahead/Carry-Select Hybrid Adder
V. Kantabutra
IEEE Trans. Computers
1993
Corpus ID: 11925005
The author presents a very fast adder for double-precision mantissas, which is an improvement on T. Lynch and E. E. Swartzlandes…
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Review
1993
Review
1993
Overview of the CHIP Compiler System
A. Aggoun
,
Nicolas Beldiceanu
Workshop on Constraint Logic Programming
1993
Corpus ID: 27206835
The MIPSpro compiler system consists of a set of components that enable you to create new 32-bit and 64-bit executable programs…
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