Skip to search formSkip to main contentSkip to account menu
BinaryConnect: Training Deep Neural Networks with binary weights during propagations
TLDR
BinaryConnect is introduced, a method which consists in training a DNN with binary weights during the forward and backward propagations, while retaining precision of the stored weights in which gradients are accumulated, and near state-of-the-art results with BinaryConnect are obtained on the permutation-invariant MNIST, CIFAR-10 and SVHN.
View PDF on arXiv
Training deep neural networks with low precision multiplications
TLDR
It is found that very low precision is sufficient not just for running trained networks but also for training them, and it is possible to train Maxout networks with 10 bits multiplications.
Low precision arithmetic for deep learning
TLDR
It is found that very low precision computation is sufficient not just for running trained networks but also for training them.
A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation
TLDR
The experimental results for the cryptanalysis of DES that are presented are based on a time-memory tradeoff using distinguished points, a method which is referenced to Rivest [2].
View via Publisher
Hardware Complexity of Modular Multiplication and Exponentiation
TLDR
This paper reviews their hardware complexity and proposes original implementations of MM and ME that become useful for 24-bit operators (Karatsuba algorithm) or 373- bit operators (FFT algorithm).
View on IEEE
Low precision storage for deep learning
TLDR
It is found that very low precision storage is sufficient not just for running trained networks but also for training them.
View PDF on arXiv
A State-Space Modeling Approach for the FPGA-Based Real-Time Simulation of High Switching Frequency Power Converters
TLDR
A comprehensive approach to the real-time simulation of power converters using a state-space representation using a new switch model that exhibits a natural switching behavior is covered in this paper.
View on IEEE
Effective floating-point calculation engines intended for the FPGA-based HIL simulation
TLDR
The effectiveness of the proposed multi-cycle accumulation scheme is here confirmed by considering a real-world application case study, that is a model of a permanent magnet synchronous motor driven by a three-phase two-level Insulated-Gate Bipolar Transistor (IGBT) inverter.
View on IEEE
An Evaluation of a High-Level Synthesis Approach to the FPGA-Based Submicrosecond Real-Time Simulation of Power Converters
TLDR
This paper evaluates the benefits of using a high-level synthesis tool to develop field-programmable gate array (FPGA)-based real-time simulators for power electronics systems and shows that HLS can be used for hardware-in-the-loop (HIL) applications when the circuit to be simulated is small and the target clock frequency is not too high.
View on IEEE
A High-Resolution Time-to-Digital Converter on FPGA Using Dynamic Reconfiguration
TLDR
A high-resolution high-precision time-to-digital converter (TDC) architecture is presented for implementation on field-programmable gate arrays (FPGAs) supporting dynamic reconfiguration and results show that the proposed architecture and calibration process can be used to achieve resolutions as fine as 10 ps.
View on IEEE
...
...
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy, Terms of Service, and Dataset License