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DIMM
Known as:
ECC DIMM RAM
, Dual In-line Memory Module
, Micro-DIMM
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A DIMM or dual in-line memory module comprises a series of dynamic random-access memory integrated circuits. These modules are mounted on a printed…
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Related topics
Related topics
50 relations
Apollo VP3
Apple Network Server
Areal density (computer storage)
Cold boot attack
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2012
2012
IBM zEnterprise redundant array of independent memory subsystem
P. Meaney
,
L. A. Lastras-Montaño
,
+5 authors
William J. Clarke
IBM Journal of Research and Development
2012
Corpus ID: 13262591
The IBM zEnterprise® system introduced a new and innovative redundant array of independent memory (RAIM) subsystem design as a…
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Highly Cited
2010
Highly Cited
2010
An efficient distributed memory interface for many-core platform with 3D stacked DRAM
Igor Loi
,
L. Benini
Design, Automation and Test in Europe
2010
Corpus ID: 14236323
Historically, processor performance has increased at a much faster rate than that of main memory and up-coming NoC-based many…
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2001
2001
Processor-memory co-exploration driven by a Memory-Aware Architecture Description Language
P. Mishra
,
P. Grun
,
N. Dutt
,
A. Nicolau
VLSI Design . Fourteenth International Conference…
2001
Corpus ID: 17254239
Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizations for programmable systems…
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1997
1997
Testing memory modules in SRAM-based configurable FPGAs
W. Huang
,
F. Meyer
,
N. Park
,
Fabrizio Lombardi
Proceedings. International Workshop on Memory…
1997
Corpus ID: 61318298
This paper studies the issues involved in testing memory modules (configured as LUTs and RAMs) in FPGAs and proposes new…
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Highly Cited
1994
Highly Cited
1994
An algorithm for array variable clustering
L. Ramachandran
,
D. Gajski
,
Viraphol Chaiyakul
Proceedings of European Design and Test…
1994
Corpus ID: 39894558
During synthesis of behavioral descriptions array variables are implemented with memory modules. In this paper we show that…
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Highly Cited
1985
Highly Cited
1985
A fault-tolerant scheme for multistage interconnection networks
N. Tzeng
,
P. Yew
,
Chuanqi Zhu
International Symposium on Computer Architecture
1985
Corpus ID: 15851689
A scheme is proposed to e n h a n c e the fault-tolerance of multistage interconnection networks which only have a unique path…
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Highly Cited
1982
Highly Cited
1982
Testing and Fault Tolerance of Multistage Interconnection Networks
D. Agrawal
Computer
1982
Corpus ID: 15237323
Test length is independent of network size in this simple, straightforward methodology for testing MINs (multistage…
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Highly Cited
1978
Highly Cited
1978
Theoretical Limitations on the Efficient Use of Parallel Memories
H. Shapiro
IEEE transactions on computers
1978
Corpus ID: 36570614
The effective utilization of single-instruction-multiple-data stream machines depends heavily on being able to arrange the data…
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Highly Cited
1976
Highly Cited
1976
Interconnections Between Processors and Memory Modules Using the Shuffle-Exchange Network
T. Lang
IEEE transactions on computers
1976
Corpus ID: 33840542
The shuffle-exchange network is considered as an interconnection network between processors and memory modules in an array…
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Highly Cited
1976
Highly Cited
1976
A Shuffle-Exchange Network with Simplified Control
T. Lang
,
H. Stone
IEEE transactions on computers
1976
Corpus ID: 206621109
In this paper, a control mechanism for a shuffle-exchange interconnection network of N cells is proposed. With this network it is…
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