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Channel-stopper
Known as:
Channel stop
, Channel stopper
, Channel-stop
In semiconductor device fabrication, channel-stopper or channel-stop is an area in semiconductor devices produced by implantation or diffusion of…
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Related topics
Related topics
2 relations
Ion implantation
Semiconductor device fabrication
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
A novel shock protection method based on MEMS compliant latching stopper
Kaisi Xu
,
N. Zhu
,
Xianfeng Zhang
,
W. Su
,
Wei Zhang
,
Y. Hao
IEEE/LEOS International Conference on Optical…
2016
Corpus ID: 26156045
This paper reports a novel shock protector on the basis of compliant latching system for the shock resistance enhancement of…
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2008
2008
On Enhancing WiMAX Hybrid ARQ: A Multiple-Copy Approach
M. Moh
,
Teng-Sheng Moh
,
Yucheng Shih
5th IEEE Consumer Communications and Networking…
2008
Corpus ID: 18718168
One major challenge in broadband wireless access networks is to provide fast, reliable services to time-sensitive communications…
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2004
2004
Closed-form expressions for the series impedance parameters of on-chip interconnects on multilayer silicon substrates
A. Weisshaar
,
A. Luoh
IEEE Transactions on Advanced Packaging
2004
Corpus ID: 24733087
This paper presents accurate closed-form expressions for the frequency-dependent series impedance parameters of on-chip…
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1997
1997
A shallow trench isolation for sub-0.13 /spl mu/m CMOS technologies
M. Nandakumar
,
S. Sridhar
,
+5 authors
I. Chen
International Electron Devices Meeting. IEDM…
1997
Corpus ID: 33595403
The design of a shallow trench isolation (STI) for sub-0.13 /spl mu/m CMOS technologies is described in this paper. The areas…
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1989
1989
An improved method for determining relative 15N abundance in ammonium regeneration studies by direct diffusion
S. Kristiansen
,
E. Paasche
1989
Corpus ID: 85006845
Ammonium in micromole quantities may be concentrated directly, with a 65% yield, from 250ml seawater into 10pl 0.25 N sulphuric…
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1987
1987
A new isolation method with boron-implanted sidewalls for controlling narrow-width effect
G. Fuse
,
M. Fukumoto
,
A. Shinohara
,
S. Odanaka
,
M. Sasago
,
T. Ohzone
IEEE Transactions on Electron Devices
1987
Corpus ID: 27127657
A new isolation method for high packing density MOS devices has been developed. In this method the LOCOS technique is applied to…
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1985
1985
Optimization of sidewall masked isolation process
C. Teng
,
G. Pollack
,
W. Hunter
IEEE Transactions on Electron Devices
1985
Corpus ID: 22829416
This paper presents modifications of the Sidewall Masked Isolation (SWAMI) process for VLSI device isolation which improve…
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1982
1982
An 8-bit, 4-phase surface channel charge-coupled device on InP
D. Lile
,
D. Collins
IEEE Transactions on Electron Devices
1982
Corpus ID: 46066244
An 8-bit, 4-phase insulated-gate CCD on bulk p-type InP is reported. The device, based on a two-level 10-µm long overlapping gate…
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1979
1979
Circuit optimization of the taper isolated dynamic gain RAM cell for VLSI memories
P. Chatterjee
,
G. Taylor
,
M. Malwah
IEEE International Solid-State Circuits…
1979
Corpus ID: 44585696
A one transistor only, ROM like dynamic RAM cell, whose operation depends on the modulation of the threshold of a buried channel…
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1977
1977
A mask programmable charge transfer analog multiplier
H. Goldberg
,
W. Engeler
,
R. Baertsch
,
J. Metz
IEEE International Solid-State Circuits…
1977
Corpus ID: 36458731
A mask-programmable four-quadrant multiplier where an analog multiplication coefficient is stored at each stage of a serial…
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