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Adder (electronics)
Known as:
Adder (electronics
, Half adder
, Carry propagation
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An adder, also called summer, is a digital circuit that performs addition of numbers.In many computers and other kinds of processors, adders are used…
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Related topics
Related topics
50 relations
4000 series
AND gate
AND-OR-Invert
ARM architecture
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2013
Highly Cited
2013
Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms
P. Whatmough
,
Shidhartha Das
,
David M. Bull
,
I. Darwazeh
IEEE Transactions on Very Large Scale Integration…
2013
Corpus ID: 15120810
In this paper, we present a novel circuit-level timing error mitigation technique, which aims to increase energy-efficiency of…
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Highly Cited
2006
Highly Cited
2006
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison
M. Alioto
,
G. Palumbo
IEEE Transactions on Very Large Scale Integration…
2006
Corpus ID: 15372256
In this paper, some of the most practically interesting full adder topologies are analyzed in terms of their delay dependence on…
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Highly Cited
2006
Highly Cited
2006
NEDA: a low-power high-performance DCT architecture
A. Shams
,
Archana Chidanandan
,
W. Pan
,
M. Bayoumi
IEEE Transactions on Signal Processing
2006
Corpus ID: 6774998
Conventional distributed arithmetic (DA) is popular in application-specific integrated circuit (ASIC) design, and it features on…
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Review
2005
Review
2005
All-optical signal Processing and applications within the esprit project DO/spl I.bar/ALL
T. Houbavlis
,
K. Zoiros
,
+12 authors
W. Miller
Journal of Lightwave Technology
2005
Corpus ID: 3078766
This paper reviews the work performed under the European ESPRIT project DO/spl I.bar/ALL (Digital OpticAL Logic modules) spanning…
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Highly Cited
2005
Highly Cited
2005
Novel design and reversible logic synthesis of multiplexer based full adder and multipliers
H. Thapliyal
,
M. B. Srinivas
Midwest Symposium on Circuits and Systems
2005
Corpus ID: 36417891
Quantum arithmetic must be built from reversible logic components. This is the driving force for the proposed novel 3/spl times/3…
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Highly Cited
2005
Highly Cited
2005
A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264
Minho Kim
,
Ingu Hwang
,
S. Chae
Proceedings of the ASP-DAC . Asia and South…
2005
Corpus ID: 15501535
We describe a fast VLSI architecture for full-search motion estimation for the blocks with 7 different sizes in MPEG-4 AVC/H.264…
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Highly Cited
2000
Highly Cited
2000
A simple processor core design for DCT/IDCT
Tian-Sheuan Chang
,
Chin-Sheng Kung
,
C. Jen
IEEE Trans. Circuits Syst. Video Technol.
2000
Corpus ID: 12561673
This paper presents a cost-effective processor core design that features the simplest hardware and is suitable for discrete…
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Highly Cited
1988
Highly Cited
1988
Variants of an Improved Carry Look-Ahead Adder
R. W. Doran
IEEE Trans. Computers
1988
Corpus ID: 9855072
An improved variation on the carry look-ahead adder has been proposed by H. Ling (IBM J. Res. Develop., vol.25, p.156, May 1981…
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Highly Cited
1987
Highly Cited
1987
Optimal Chaining of CMOS Transistors in a Functional Cell
S. Wimer
,
R. Pinter
,
J. Feldman
IEEE Transactions on Computer-Aided Design of…
1987
Corpus ID: 16227281
We describe an algorithm that maps a CMOS circuit diagram into an area-efficient, high-performance layout in the style of a…
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Highly Cited
1985
Highly Cited
1985
Some optimal schemes for ALU implementation in VLSI technology
V. Oklobdzija
,
E. Barnes
IEEE Symposium on Computer Arithmetic
1985
Corpus ID: 18948775
An efficient scheme for carry propagation in an ALU implemented in n-MOS technology is presented. An algorithm that determines…
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